0adb604c97
Merge pull request #1423 from zyp/improve_dma
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Improve DMA
2022-09-14 09:57:43 +02:00
89bb688500
Merge pull request #1426 from enjoy-digital/naxriscv-merge
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cpu/NaxRiscv fix peripheral bus width to 32 bits and CLINT is now protected from overflow glitches
2022-09-12 23:25:47 +02:00
0a380b9c3b
cpu/NaxRiscv improve peripheral read/write speed by staying 32 bits
2022-09-12 19:19:35 +02:00
8e7fd9bc1f
Merge branch 'master' into naxriscv-merge
2022-09-12 19:18:12 +02:00
23f529a313
soc/builder: Propagate data_width to get_mem_data.
2022-09-12 16:46:20 +02:00
481234de91
integration/common/get_mem_data: Add data_width support.
2022-09-12 16:45:55 +02:00
a7cc1af416
soc: Propagate main bus address_width to the different interfaces dynamically created.
2022-09-12 16:13:45 +02:00
95bed6de5c
interconnect/wishbone: Allow passing address_width (In byte addressing).
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This is useful to abstract interfaces and propagate address_width.
Idealy, Wishbone should be fully switch to byte addressing since word addressing
has been a source of common issues/errors in the past but compatibility issues
would need to be evaluated first.
2022-09-12 16:12:52 +02:00
91c521a22a
Changes: Prepare for next release changes.
2022-09-12 11:08:50 +02:00
ded3bad178
cpu/naxriscv: Minor cleanups on recent changes.
2022-09-12 11:01:42 +02:00
f2a088bfcc
Merge pull request #1355 from cklarhorst/master
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integration/soc Add accessible_region to add_memory_buses
2022-09-12 10:18:22 +02:00
fa0c2df687
CHANGES: Update and release.
2022-09-12 09:00:36 +02:00
3c4c12a72f
cores/dma: End transfer when the last flag is set.
2022-09-10 10:15:37 +02:00
6ad6d1e414
cores/dma: Don’t drop data while idle.
2022-09-10 10:15:37 +02:00
6367fc6cab
update naxriscv comments
2022-09-09 13:19:36 +02:00
15f72174ce
interconnect/axi/axi_full: Add region signal to aw/ar and optional user signal to aw/w/b/ar/r channels.
2022-09-09 12:46:31 +02:00
14160ce7e3
cpu/NaxRiscv update nax with peripheral memory region
2022-09-09 11:23:24 +02:00
b7e2d24f37
interconnect/wishbone/DownConverter: Avoid FSM and Idle cycle.
2022-09-08 17:41:24 +02:00
a04f20880f
Change naxriscv memory-region format
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It now has a mode and a bus field.
modes: rwxc (read, write, execute, cachable)
bus: pm (peripheral, memory)
2022-09-08 17:33:20 +02:00
e5de4b356a
interconnect/axi/axi_lite: Add prot signal.
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Not directly used by LiteX but useful for wrapping AXI-Lite RTL code.
2022-09-08 12:06:35 +02:00
3b714c8145
test: Add minimal test_axi_stream test (Just syntax check for now).
2022-09-08 11:53:05 +02:00
afc89c9350
interconnect/axi/axi_stream: Add ID/Dest support and minor cleanup.
2022-09-08 11:51:55 +02:00
5b8d3651a9
software/liblitedram: Enable ECP5DDRPHY features on GW2DDRPHY (since very similar).
2022-09-07 16:27:54 +02:00
ee536f9cd5
CONTRIBUTORS: Update.
2022-09-07 10:13:17 +02:00
85e8aab5ae
tools/litex_contributors: Sort contributors by names.
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The git .csv generation is already sorted but this needs to be sorted again due
to the companies renaming.
2022-09-07 10:07:12 +02:00
0bd19fd026
tools/litex_contributors: Rename authors to contributors.
2022-09-07 09:49:26 +02:00
0144612751
tools/litex_contributors: Add RapidSilicon to companies.
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RapidSilicon is helping funding the improvement/development of LiteX features
and the team also contribute directly to the project.
2022-09-07 09:48:27 +02:00
4d6813ae64
tools/litex_contributors: Sort years.
2022-09-07 09:42:20 +02:00
a6acfb9a37
stream/Buffer: Integrate PipeValid/PipeReady (both configurable) and add tests.
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Allow selecting pipelining of valid/data or/and ready and creating a full Skid Buffer
(Pipeline of both valid/data and ready).
2022-09-07 08:59:37 +02:00
ce90181046
cpu/VexRiscv_SMP add --wishbone-force-32b option
2022-09-06 13:13:45 +02:00
af43e98e78
Merge branch 'naxriscv-merge'
2022-09-06 13:07:54 +02:00
5fad94f9d6
cpu/VexRiscv_SMP add --wishbone-force-32b option
2022-09-06 11:23:36 +02:00
36297c7a1e
cores/video: Avoid serializer_attrs.
2022-09-05 09:49:15 +02:00
398811b910
Merge pull request #1413 from trabucayre/gowin_HDMI
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soc/cores/video: adding Gowin HDMI Phy
2022-09-05 09:32:29 +02:00
8159b5caad
Merge pull request #1412 from umarcor/umarcor/f4pga
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litex/build/xilinx/f4pga: update imports
2022-09-02 19:03:02 +02:00
a9c7e868e7
soc/cores/video: adding Gowin HDMI Phy
2022-09-02 19:00:33 +02:00
7f17866386
litex/build/xilinx/f4pga: update imports
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Signed-off-by: umarcor <umartinezcorral@antmicro.com>
2022-09-02 15:48:22 +02:00
153182a014
cores/dna: Fix typo.
2022-09-02 13:09:40 +02:00
c8bd747e0f
Remove linker regions from naxriscv mem list
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Assume linker=True SoCRegions are virtual only.
2022-09-02 12:13:21 +02:00
4426e61899
soc/add_pcie: Expose with_synchronizer parameter.
2022-09-01 17:47:27 +02:00
b24d744f8e
cores/dna: Rewrite/simplify core and use a slower clock (sys_clk/16).
2022-09-01 14:24:01 +02:00
1c4d64f46b
CHANGES: Update.
2022-09-01 11:22:25 +02:00
b63e445ade
cpu/NaxRiscv: Update to new version
2022-08-31 15:31:37 +02:00
6cbeed6f73
Merge branch 'enjoy-digital:master' into master
2022-08-31 13:27:32 +02:00
fb2a52a6c7
Generate naxriscv mem region parameters in new format
2022-08-31 13:25:27 +02:00
c0d3775dcd
integration/builder: Simplify bios_console.
2022-08-31 12:10:15 +02:00
aec02b395d
integration/builder: Add default bios_console value.
2022-08-31 10:33:26 +02:00
35afd59956
tools/litex_server/litex_client: Add initial information exchange and improve PCIe case.
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Due to the address translation done with the LitePCIe bridge (remapping CSR to 0), RemoteClient
needs to know which bridge is used to also translate CSRs.
This commit adds an initial information exchange between server and client and avoid the PCIe workarounds.
2022-08-30 18:54:03 +02:00
027306972a
Naxriscv now scans for executable mem regions and forwards that info to the scala build process
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Format:
--scala-args=executable-region=(origin, length), --scala-args=exe...
2022-08-30 16:41:39 +02:00
3e42133abd
Change SDRAM region to RWX
2022-08-30 16:22:29 +02:00
enjoy-digital
Dolu1990
Vegard Storheil Eriksen
Christian Klarhorst
Gwenhael Goavec-Merou
umarcor
Christian Klarhorst