3ebe877fd2
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
c03c41eb77
litescope: rename host directory to software (to be coherent with others cores)
2015-05-01 20:45:02 +02:00
1281a463d6
litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
...
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
d253adee61
liteeth: use Migen's Packetizer/Depacketizer, remove generic and move etherbone/tty to frontend
2015-04-28 18:51:40 +02:00
91c77d464c
liteeth: use new Migen modules from actorlib (avoid duplications between cores)
2015-04-27 15:06:37 +02:00
5a930fe7cf
lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file
2015-04-18 08:51:59 -04:00
2bd38f44a3
liteeth: more pep8 (when convenient), should be almost OK
2015-04-13 13:02:04 +02:00
154d3d3b04
liteeth: pep8 (E265)
2015-04-13 11:27:01 +02:00
45dc4920ec
liteeth: pep8 (E261, E271)
2015-04-13 11:07:50 +02:00
a84f12618b
liteeth: pep8 (E225)
2015-04-13 10:56:18 +02:00
66ce40d880
liteeth: pep8 (E222)
2015-04-13 10:48:59 +02:00
ff2d7f9adc
liteeth: pep8 (E401)
2015-04-13 10:45:09 +02:00
5720638d85
liteeth: pep8 (E302)
2015-04-13 10:20:02 +02:00
cd43eaffc2
liteeth: pep8 (replace tabs with spaces)
2015-04-13 09:53:43 +02:00
dcdf5df4de
adapt LiteEth to new SoC
2015-04-01 22:50:29 +02:00
9107710f03
litexxx cores: use default baudrate of 115200 for all tests
2015-03-20 12:22:53 +01:00
236ea0f572
liteeth: use bios ip_address in example designs
2015-03-18 18:18:43 +01:00
a266deb58e
LiteXXX cores: fix frequency print in test/test_regs.py
2015-03-17 16:01:25 +01:00
d2cb41bc63
LiteXXX cores: convert port parameter to int if is digit in test/make.py
2015-03-17 15:58:21 +01:00
408d0fd2dd
liteeth: use default programmer in make.py
2015-03-17 12:12:21 +01:00
ec6ae75065
liteeth: use CRG from Migen in base example
2015-03-17 12:11:51 +01:00
52f1c45407
LiteXXX cores: fix test_reg.py
2015-03-04 23:13:14 +01:00
1d4dc45436
LiteXXX cores: use format in prints
2015-03-03 10:29:28 +01:00
649cdeb265
liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
2015-03-01 16:48:41 +01:00
c21a7956c8
liteXXX cores: remove Identifier duplication
2015-03-01 11:24:58 +01:00
67ca0da1d9
liteXXX cores: share same methodology for on-board tests
2015-03-01 11:21:12 +01:00
b32a0e6f9e
liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins
2015-02-28 23:33:00 +01:00
b34be816ec
liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH)
2015-02-28 22:23:48 +01:00
5c43d4d091
litescope: create example design derived from SoC that can be used on all targets
2015-02-28 22:19:24 +01:00
0fd1b9df8d
liteXXX cores: remove redefinition of get_csr_csv
2015-02-28 21:45:05 +01:00
69e869893d
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
2015-02-28 11:36:15 +01:00
2c3e8a2804
liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)
2015-02-28 11:04:48 +01:00
df0ba1b03c
litescope: create example_designs directory
2015-02-28 10:42:12 +01:00
c4ebf244a1
litescope: move files and modify import to misoclib.tools.litescope
2015-02-28 10:33:46 +01:00
2c51adcd68
misoclib: better organization (create cores categories: cpu, mem, com, ...)
2015-02-28 09:40:44 +01:00
Florent Kermarrec