5c5bc82f22
interconnect/packet/PacketFIFO: Fix payload_fifo.sink.valid.
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Needs to be filtered on param_fifo.sink.ready and not payload_fifo.sink.ready.
2024-07-26 11:52:17 +02:00
dc04949d78
build/altera/common,platform: added ddrinput/ddrout primitives
2024-07-25 14:11:06 +02:00
c51d22074f
soc/integration/soc/add_uart: Allow directly passing uart_pads.
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Useful for test purpose when testing multiple UART peripherals without having to expose them on IOs.
2024-07-22 16:23:22 +02:00
b8cb6da2b9
soc/cores/clock/lattice_nx.py: added clk contraints for OSCA output
2024-07-22 15:11:40 +02:00
ecd0f0e548
cores/ram/lattice_nx: Revert #1906 since not working with RAM combining multiple SP512K.
2024-07-22 14:24:34 +02:00
4662b95f16
Merge pull request #2012 from machdyne/master
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soc/cores/video: Add additional color formats
2024-07-21 09:34:00 +02:00
4301293b21
Merge pull request #2018 from motec-research/add_i2c_master
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Add i2c master
2024-07-21 09:32:48 +02:00
67e6614eb2
test_i2c: whitespace cleanups
2024-07-20 15:45:44 +10:00
643f3f9a93
test_i2c: add more commands
2024-07-20 15:45:44 +10:00
f99658200e
soc/cores/i2c: rewrite state machine
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* Fix READ: was reading too many bits
* CLeaner transitions between states: ACK=>IDLE with scl=0. Other to IDLE with scl=1
* Now cleanly supports RESTART
* conceptual support for compound commands - not exposed yet
* fix tests: now appears to be I2C compliant
2024-07-20 15:45:44 +10:00
13811aeacb
test_i2c: update to use improved _MockTristate
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* test now checks the actual i2c bus state, not the I2CMaster output
* refactor to eliminate some copy/paste
* tests now work again with this change: 'only change SDA when SCL is stable'
2024-07-20 15:45:44 +10:00
b779933a5f
test_i2c: improve and document _MockTristate*
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Added i_mock for simulated external device:
* when _oe = 0 _i = _i_mock
* when _oe = 1 _i = _o
2024-07-20 15:45:44 +10:00
dce152b348
soc/cores/i2c: change SDA 1 or 2 cycles earlier
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* update 'only change SDA when SCL is stable' to max 1 sys_clk delay
2024-07-20 15:45:44 +10:00
e36946b251
soc/cores/i2c: convert to LiteXModule and name some components
2024-07-20 15:45:44 +10:00
c867d5647b
soc/cores/i2c: only change SDA when SCL is stable
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Avoid changing SDA immediately in states WRITE0 and READ0 to guarantee SDA hold is > 0
2024-07-20 15:45:44 +10:00
aef6cb3103
soc/cores/i2c: remove unnecessary code
2024-07-20 15:45:44 +10:00
64ccd6df1c
test_i2c: allow unit test to run directly
2024-07-20 15:45:44 +10:00
5504cc626f
soc/cores/i2c: change ISR to rising edge of idle
2024-07-20 15:45:44 +10:00
b8b6ecef7c
soc/cores/i2c: fix CSR generation
2024-07-20 15:45:44 +10:00
90128756f9
test_i2c: test reading config
2024-07-20 15:45:44 +10:00
ad37e17743
soc/cores/i2c: add interrupt
2024-07-20 15:45:44 +10:00
4ddab34714
test_i2c: generate i2c.vcd
2024-07-20 15:45:44 +10:00
a079da922a
soc/cores: adapt misoc i2c to litex
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Also add misoc license information.
2024-07-20 15:45:44 +10:00
9dc3eefb7d
soc/cores/i2c: import from misoc
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* unmodified - integration to follow
* from: https://github.com/m-labs/misoc @ 26f039f Dec 2022
2024-07-20 15:45:44 +10:00
a014c4f07c
tools/litex_sim: Cleanup imports.
2024-07-18 12:16:23 +02:00
8a08d5ca19
Merge pull request #2017 from Dolu1990/vexiiriscv
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Fix VexiiRiscv
2024-07-18 11:37:03 +02:00
cbe7413fee
Fix VexiiRiscv
2024-07-18 11:32:07 +02:00
1b9bdbdce4
Merge pull request #2016 from Dolu1990/vexiiriscv
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Update VexiiRiscv
2024-07-18 11:27:20 +02:00
f687425cb1
Update VexiiRiscv
2024-07-18 11:26:13 +02:00
473784581d
Merge pull request #2011 from Dolu1990/vexiiriscv
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cpu: Vexii/Nax fmax / area improvements
2024-07-12 17:29:45 +02:00
9fa1b4c123
Update Nax/Vexii
2024-07-12 16:17:30 +02:00
aef5a2094e
soc/cores/video: Add additional color formats
2024-07-10 15:21:51 +02:00
22ff3ac42d
Merge branch 'master' into vexiiriscv
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# Conflicts:
# litex/soc/cores/cpu/vexiiriscv/core.py
2024-07-10 09:37:43 +02:00
1267ba8ae6
Update Nax/Vexii
2024-07-10 09:35:34 +02:00
e4e9bd2125
interconnect/axi/axi_lite: Add bursting property even if always False.
2024-07-09 17:02:54 +02:00
372ab25273
Merge branch 'nax64_irq' into vexiiriscv
2024-07-09 15:18:25 +02:00
549d23e4f7
build/efinix: Add default parameter values and fix other typos.
2024-07-09 10:04:03 +02:00
e6171e79db
build/efinix: Fix typos (thanks @AndrewD).
2024-07-09 10:00:21 +02:00
7de4f01aa8
Merge pull request #2009 from trabucayre/efinix_args_opts
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build/efinix: added argument to change synthesis options configurations
2024-07-08 17:01:28 +02:00
ec1528fb69
build/efinix: added argument to change synthesis options configurations
2024-07-08 15:59:30 +02:00
0db650ac6a
soc/interconnect/stream: Improve MonitorCounter timings (avoid reset, clearer logic).
2024-07-05 13:56:14 +02:00
3c2ddd1655
cores/can/ctu_can_fd: Remove pads.irq that was used as debug.
2024-07-05 09:34:36 +02:00
7ec35eb4c5
Merge pull request #2007 from enjoy-digital/ctu-can-fd
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Add initial CTU-CAN-FD core support.
2024-07-05 09:16:21 +02:00
d838a9ca73
Merge pull request #2006 from trabucayre/update_altera_build
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Update altera build
2024-07-04 13:04:15 +02:00
9fd63973aa
build/altera/quartus.py: added support for ips other than QSYS_FILE
2024-07-04 09:51:09 +02:00
7393c35264
build/altera/platform,quartus: allows user to select Analysis&Synthesis tool (quartus_map (default) or quartus_syn
2024-07-04 09:50:06 +02:00
b286fe5621
Merge pull request #2005 from VOGL-electronic/json2dts_zephyr_remove_configs
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litex_json2dts_zephyr.py: Remove unnessesary configs
2024-07-04 09:10:27 +02:00
d4d1a1bfd7
gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.
2024-07-03 21:44:31 +02:00
aac828b4cb
soc/add_etherbone: Update ethmac.
2024-07-02 17:10:32 +02:00
b285992fb1
litex_json2dts_zephyr.py: Remove unnessesary configs
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Remove all configs, that are enabled by default
in zephyr based on the devicetree.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-07-02 15:04:50 +02:00
Florent Kermarrec
Gwenhael Goavec-Merou
Andrew Dennison
Radek Pesina
Richard Tucker
Dolu1990
inc
Fin Maaß