06f3c46e35
genlib/misc: fix missing *args in Counter
2015-03-04 23:49:15 +01:00
3d7f9fd685
mibuild/sim/server_tb: use SERIAL_SINK_ACK
2015-03-04 00:55:35 +01:00
2d6fbd7902
mibuild/sim: use /tmp/simsocket sockaddr for server
2015-03-03 22:52:28 +01:00
f4b060f6fe
mibuild/sim: avoid updating end at each cycle (simulation speedup)
2015-03-03 18:01:14 +01:00
5ec26a49c3
mibuild/sim: simplify console_tb with sim struct
2015-03-03 17:57:58 +01:00
991572f4fe
mibuild/sim: create server.py and server_tb (Proof of concept OK with flterm)
...
Using a server allow us to create a virtual UART (and ethernet TAP in the future).
1) start the server
2) start flterm on the virtual serial port created by the server
3) run the simulation
This will enable us to do serialboot and netboot in simulation.
This will also enable prototyping ethernet for ARTIQ in simulation.
2015-03-03 17:38:22 +01:00
f154c2e7ec
xilinx/programmer/vivado: fix Linux support
2015-03-03 02:06:39 +00:00
154ad54a8e
platforms/kc705: fix imports
2015-03-03 02:03:14 +00:00
a56fce045b
Merge branch 'master' of http://github.com/m-labs/migen
2015-03-02 23:24:48 +01:00
29c5bb8bcd
mibuild/sim/verilator: remove verilator_root, use -Wno-fatal and add verbose option (verbose disabled by default)
2015-03-02 23:23:23 +01:00
36f4b68dd8
mibuild/sim: style fixes
2015-03-02 21:56:20 +00:00
7d68ecbd86
move dma_lasmi to MiSoC
2015-03-02 08:23:02 +01:00
58290f3c43
lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
2015-03-01 22:04:20 +01:00
382ca374c3
mibuild: initial Verilator support
2015-03-01 18:27:46 +01:00
8f81ae6826
genlib/misc: add FlipFlop, Counter, Timeout
2015-03-01 16:33:46 +01:00
961b4bfb4c
platforms/pipistrello: remove unconnected SDRAM pins
2015-02-28 16:20:44 -07:00
03431ece9f
pipistrello: fix ddram dqs, cleanup constraints, add pullup/downs
2015-02-28 16:16:47 -07:00
75290aa0f3
pipistrello: switch back to xc3sprog and fast (papilio) speed
2015-02-28 16:16:47 -07:00
eb8ba145de
kx705: add programmer parameter
2015-02-28 23:34:57 +01:00
b53e2b0d6e
fix xilinx/programmer with Vivado
2015-02-28 19:33:20 +01:00
87d8ff2de7
xilinx/programmer: add source of vivado's settings (need to be tested on a linux machine)
2015-02-28 03:38:47 +01:00
e82531cdf8
move dfi/lasmibus/wishbone2lasmi to MiSoC sdram
2015-02-27 16:54:22 +01:00
225a2d4704
report cachesize in wishbone2lasmi
2015-02-27 14:12:13 +01:00
54a8a52e90
xilinx/programmer: add partial flash_bitstream for vivado (can flash full bitstream, need to be adapted to flash part of the flash (bios, ...))
2015-02-27 09:05:23 +01:00
2b0937153d
xilinx/programmer: fix xc3sprog (GenericProgrammer)
2015-02-26 21:36:15 -07:00
8de5b947bd
pipistrello: use fpgaprog
2015-02-26 21:34:02 -07:00
ca52aa5b8c
add fpgaprog programmer
2015-02-26 21:33:49 -07:00
5b5d2d15b8
add pipistrello platform
2015-02-26 21:33:42 -07:00
ba26a400e3
Merge branch 'master' of https://github.com/m-labs/migen
2015-02-26 21:32:39 -07:00
28c219ebd2
platforms/kc705: add user SMA clock
2015-02-26 16:22:22 -07:00
dbdb263acc
mibuild/kc705: add missing pins on FMC LPC
2015-02-26 15:54:41 -07:00
8da1faf310
mibuild: move identifier to platforms
2015-02-26 19:00:43 +01:00
e6a21b2305
mibuild: fix missing xilinx_common -->xilinx.common change
2015-02-26 14:04:36 +01:00
bd5ed0977b
platforms: add default_clk_freq/default_clk_name (to use it on simple designs to test MiSOC on various platforms)
2015-02-26 12:51:57 +01:00
e27a94e7fc
mibuild: add VivadoProgrammer (only load_bitstream)
2015-02-26 12:31:19 +01:00
b3faf5f0da
mibuild: better file organization (create directory for each vendor and move programmers in it)
2015-02-26 12:25:59 +01:00
5bb1c789aa
mibuild/kc705: add FMC connectors
2015-02-18 08:32:45 -07:00
cea1551ae0
mibuild: support pin names in IO extensions
2015-02-18 08:32:31 -07:00
452c60e0c3
endpoints: add param_layout parameter (required to pass parameter data with converters and will allow logic optimizations)
2015-02-14 03:10:56 -08:00
319465445d
actorlib/structuring: fix eop generation in Pack
2015-02-14 03:07:18 -08:00
d51d33af73
mibuild: make resolve_signals public
2015-02-14 03:05:07 -08:00
beef7425ce
mibuild: return verilog namespace with build
2015-02-14 03:02:47 -08:00
c7eba8f4c4
remove crc since each crc is specific. It's probably better to adapt code for each case.
2015-02-14 03:01:12 -08:00
7471b2a152
genlib/crc: use OrderedDict
2015-01-23 00:23:41 +08:00
2175a79c03
fhdl/std: add FinalizeError import
2015-01-23 00:23:41 +08:00
6fca1dd4dc
mibuild/xilinx_vivado: fix list aliasing problem
2014-12-21 17:37:11 +08:00
8576b91290
xilinx_vivado: add parameters to pass specific commands (to be declared in platforms)
2014-12-21 17:35:42 +08:00
037ea05b1e
crc: modify CRCChecker to remove CRC and clean up
2014-12-21 17:24:52 +08:00
ae770c0f8c
bank: support direct mapping of CSRs on Wishbone
2014-11-30 22:28:39 +08:00
ee928a8973
Wishbone DownConverter: Fix sel signal
2014-11-26 19:33:12 +08:00
Florent Kermarrec
Sebastien Bourdeauducq
Robert Jordens
Yann Sionneau