f7969b660a
cores/clock: add with_reset parameter (default to True)
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In some cases we want to generate the reset externally.
2018-10-31 16:23:23 +01:00
0729b3a059
ulx3s: Connect SDRAM clock
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-31 13:29:35 +00:00
8404434956
Fix Trellis build; ULX3S demo boots to BIOS
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-31 12:27:05 +00:00
0c1d8d5993
trellis: Switch to using LPF for constraints
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-31 11:43:39 +00:00
445c49400f
boards/platforms/kcu105: add sfp_tx/rx definition
2018-10-31 10:48:48 +01:00
f69bd877b9
cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations).
2018-10-30 06:00:45 -04:00
d05fe673a0
cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs.
2018-10-30 06:00:45 -04:00
e9d4c882ba
build/lattice/prjtrellis: fix default toolchain_path
2018-10-30 10:28:12 +01:00
468780c045
soc/cores/spi_flash: add endianness parameter
2018-10-30 10:19:21 +01:00
6f3131e259
soc/interconnect/stream_packet: use reverse_bytes from litex.gen
2018-10-30 10:16:55 +01:00
b796853893
gen: add common with reverse_bits/reverse_bytes functions
2018-10-30 10:15:29 +01:00
71fc34d7b6
boards/targets/ulx3s: reduce l2_size
2018-10-30 10:14:48 +01:00
75d073f394
build/lattice/prjtrellis: fix typo
2018-10-30 10:14:30 +01:00
6048a5291c
build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper, handle inouts.
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nextpnr expects TRELLIS_IO on all ios, it's not possible to ensure that with a wrapper.
We now just modify the generated verilog to insert the io constraints and TRELLIS_IOs.
2018-10-30 08:54:30 +01:00
2243f628f7
build/lattice/common: fix LatticeECPXPrjTrellisTristateImpl
2018-10-30 08:47:12 +01:00
3a8bb94ab4
Merge pull request #121 from cr1901/patch-3
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Update vivado.py
2018-10-29 20:54:23 -07:00
f3111e1142
Update vivado.py
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Fix regression which caused Vivado to not be run at all.
2018-10-29 23:43:32 -04:00
98fa899692
boards/targets: add ulx3s
2018-10-29 19:24:28 +01:00
7d779473f1
boards/platforms: add ulx3s
2018-10-29 19:23:59 +01:00
d9dcad33a4
build/lattice/prjtrellis: add inout support
2018-10-29 19:23:21 +01:00
091ad799b0
build/lattice/common: add tristate support
2018-10-29 19:22:04 +01:00
23acefb14e
boards/targets/versaecp55g_prjtrellis: simple.py example working, specific target no longer needed
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simple.py configuration tested:
python3 simple.py --cpu-type=lm32 --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
python3 simple.py --cpu-type=vexriscv --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
2018-10-29 16:02:25 +01:00
1097f82283
build/lattice/prjtrellis: set default toolchain_path to "/opt/prjtrellis"
2018-10-29 15:58:54 +01:00
52917a710e
boards/targets/simple: add gateware-toolchain parameter
2018-10-29 15:56:46 +01:00
d84083f642
boards/platforms/versaecp55g: use ftdi serial pins
2018-10-29 15:39:51 +01:00
c05b9ef2ad
build/lattice/prjtrellis: test and fix iowrapper multi-bit signals support
2018-10-29 13:26:29 +01:00
a8f819fec2
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-10-29 11:48:10 +01:00
4eb314a252
boards/targets/versaecp55g: use new iowrapper support, basic led blink and ios working :)
2018-10-29 11:46:03 +01:00
27ec2a59e2
build/lattice/prjtrellis: generate iowrapper to set constraints and TRELLIS_IO
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PrjTrellis does not yet have constraint files support, constraints are set
with signal attributes and specific TRELLIS_IO instances are requested. This
iowrapper does this work for us automatically.
Remove this code and replace with a constraint file generation code when
PrjTrellis will have constraint file support.
2018-10-29 11:44:31 +01:00
c506c9752c
gen/fhdl/verilog: set direction to io signals
2018-10-29 11:41:04 +01:00
9815920946
Merge pull request #120 from mithro/master
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litex/build: Always run Vivado.
2018-10-29 02:08:20 -07:00
1cac079efa
litex/build: Always run Vivado.
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When using Yosys for synthesis, still need Vivado for place and route.
2018-10-29 02:04:44 -07:00
49dab3b448
build/lattice/prjtrellis: simplify code, remove some workarounds
2018-10-29 09:40:35 +01:00
a73d9d96b1
build/xilinx/vivado: fix merge issue
2018-10-29 08:26:13 +01:00
3e189379f9
boards/targets: add versa ecp55g prjtrellis target (experimental)
2018-10-28 19:34:17 +01:00
a69197d2db
build/lattice: add initial prjtrellis support
2018-10-28 17:51:16 +01:00
397e3c7682
build/lattice/diamond: use bash on linux
2018-10-28 15:40:52 +01:00
d029cd243d
build/lattice: improve special_overrides names (vendor_family)
2018-10-28 15:40:10 +01:00
60665358d4
Merge pull request #114 from mithro/xilinx+yosys
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WIP: Allow Yosys to be used for synthesis with Vivado
2018-10-28 15:00:06 +01:00
b200ce9983
Merge branch 'master' into xilinx+yosys
2018-10-28 14:59:03 +01:00
8c0982a1d5
Merge pull request #118 from mithro/uart-sync
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uart: Enable buffering the FIFO.
2018-10-28 08:02:22 +01:00
ba0dd5728e
uart: Enable buffering the FIFO.
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On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
2018-10-27 16:04:58 -07:00
f916705313
README: improve instructions for litex_sim
2018-10-27 11:06:53 +02:00
e3935b481e
build/sim/verilator: don't use THEADS parameters when threads=1
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Allow using old (non multi-threaded) version of Verilator
2018-10-27 11:06:34 +02:00
a44181e716
soc_sdram: update litedram
2018-10-19 18:37:55 +02:00
ab6a530a24
bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode
2018-10-18 13:42:51 +02:00
b8be9545cc
build/xilinx/vivado: enable xpm libraries
2018-10-18 09:25:34 +02:00
ab8cf3e345
soc/cores/clock: add margin parameter to create_clkout (default = 1%)
2018-10-16 14:57:37 +02:00
915c2f417a
bios/sdram: improve write/read leveling
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write_leveling: select last 0 to 1 transition.
read_leveling: do it by module (select best bitslip for each module)
2018-10-10 10:42:56 +02:00
deffa60324
platforms/kc705: add ddram_dual_rank
2018-10-09 15:39:03 +02:00
Florent Kermarrec
David Shah
William D. Jones
Tim Ansell