Sebastien Bourdeauducq
|
c3fdf42825
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bus/csr: add SRAM
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2012-12-06 17:16:17 +01:00 |
|
Sebastien Bourdeauducq
|
4bcb39699b
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bus/wishbone/sram: accept memories < 32 bits
|
2012-12-01 13:04:22 +01:00 |
|
Sebastien Bourdeauducq
|
523816982a
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bus/wishbone: add SRAM
|
2012-12-01 12:59:09 +01:00 |
|
Sebastien Bourdeauducq
|
d8e478efee
|
Replace Signal(bits_for(... with Signal(max=...
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2012-11-29 21:53:36 +01:00 |
|
Sebastien Bourdeauducq
|
50ed73c937
|
New specification for width and signedness
|
2012-11-29 21:22:38 +01:00 |
|
Sebastien Bourdeauducq
|
fee22a4631
|
Remove Constant
|
2012-11-28 23:18:43 +01:00 |
|
Sebastien Bourdeauducq
|
5183774ec8
|
bus/wishbone2asmi: do not use MemoryPort
|
2012-11-26 19:14:59 +01:00 |
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Sebastien Bourdeauducq
|
ab31b4d99c
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bus: memory initiator
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2012-11-23 16:22:50 +01:00 |
|
Sebastien Bourdeauducq
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d4baac6c0f
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bus/csr: allow specifying existing interface
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2012-11-17 19:44:25 +01:00 |
|
Sebastien Bourdeauducq
|
86090e1cbd
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bus/asmibus: swap port position to be consistent with wishbone API
|
2012-11-17 19:42:39 +01:00 |
|
Sebastien Bourdeauducq
|
ece786d6aa
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bus/wishbone: allow specifying existing interface
|
2012-11-17 19:42:06 +01:00 |
|
Sebastien Bourdeauducq
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d0d4c48098
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bus/transactions: add busname parameter
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2012-11-17 19:36:08 +01:00 |
|
Sebastien Bourdeauducq
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4164fb4ac9
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bus/csr: configurable data width
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2012-08-26 21:19:34 +02:00 |
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Sebastien Bourdeauducq
|
8de192dfbd
|
x.bv.width -> len(x)
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2012-07-13 18:32:54 +02:00 |
|
Sebastien Bourdeauducq
|
b4613d913f
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bus/wishbone: remove use of deprecated multimux
|
2012-07-13 17:17:20 +02:00 |
|
Sebastien Bourdeauducq
|
8062e48697
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bus/asmibus: fix per-port tag generation
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2012-07-12 19:37:50 +02:00 |
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Sebastien Bourdeauducq
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c82a468506
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bus: CSR initiator
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2012-07-07 22:36:15 +02:00 |
|
Sebastien Bourdeauducq
|
8a23451237
|
PureSimulable
|
2012-06-12 17:08:56 +02:00 |
|
Sebastien Bourdeauducq
|
a591510189
|
ASMI simulation models
|
2012-06-12 16:57:00 +02:00 |
|
Sebastien Bourdeauducq
|
b7a84b3750
|
wishbone: base TargetModel class
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2012-06-10 17:05:10 +02:00 |
|
Sebastien Bourdeauducq
|
ec501e7797
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bus/wishbone: target model
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2012-06-10 16:40:33 +02:00 |
|
Sebastien Bourdeauducq
|
f061b25a24
|
bus/wishbone/Tap: remove ack feature
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2012-06-10 12:46:24 +02:00 |
|
Sebastien Bourdeauducq
|
11674242c4
|
Use super() instead of calling parent constructors directly
|
2012-06-08 18:06:12 +02:00 |
|
Sebastien Bourdeauducq
|
68cd445662
|
bus/wishbone2asmi: fix cache tag size
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2012-05-15 15:18:03 +02:00 |
|
Sebastien Bourdeauducq
|
0bea1e2589
|
asmi: dat_wm high to disable data write
|
2012-05-15 14:41:54 +02:00 |
|
Sebastien Bourdeauducq
|
f2c20e4af0
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bus/asmibus/hub: hack to prevent comb loops
|
2012-04-30 17:11:42 -05:00 |
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Sebastien Bourdeauducq
|
6e3b25ebb6
|
bus/dfi: reset active low signals to 1
|
2012-04-01 17:43:24 +02:00 |
|
Sebastien Bourdeauducq
|
94b02aa8ed
|
bus/asmicon: initiator
|
2012-03-30 22:16:31 +02:00 |
|
Sebastien Bourdeauducq
|
e969b9afc3
|
corelogic: convert timeline to function and move to misc
|
2012-03-15 20:25:44 +01:00 |
|
Sebastien Bourdeauducq
|
1665f293a6
|
bus/asmibus/hub: require finalization before get_slots
|
2012-03-14 16:19:29 +01:00 |
|
Sebastien Bourdeauducq
|
5c0cc6292c
|
fhdl: export log2_int
|
2012-03-14 12:19:42 +01:00 |
|
Sebastien Bourdeauducq
|
ab800fa2ed
|
bus: generic transaction model
|
2012-03-08 18:14:06 +01:00 |
|
Sebastien Bourdeauducq
|
1b8cb5b46c
|
bus/dfi: fix multiphase naming
|
2012-02-19 17:57:04 +01:00 |
|
Sebastien Bourdeauducq
|
92dfbb92dd
|
bus: add interconnect statements function
|
2012-02-17 23:51:32 +01:00 |
|
Sebastien Bourdeauducq
|
c08687b9c6
|
bus/dfi: filter signals by direction
|
2012-02-15 21:48:05 +01:00 |
|
Sebastien Bourdeauducq
|
fa9cf3e466
|
bus: add DFI
|
2012-02-15 18:09:14 +01:00 |
|
Sebastien Bourdeauducq
|
af5230c8ee
|
bus: fix simple interconnect
|
2012-02-15 16:42:05 +01:00 |
|
Sebastien Bourdeauducq
|
0493212124
|
bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
|
2012-02-15 16:30:16 +01:00 |
|
Sebastien Bourdeauducq
|
46b1f74e98
|
bus/asmibus/hub: forward data and tag_call
|
2012-02-14 14:00:17 +01:00 |
|
Sebastien Bourdeauducq
|
0c214b484e
|
Use double quotes for all strings
|
2012-02-14 13:12:43 +01:00 |
|
Sebastien Bourdeauducq
|
e11d9b9322
|
bus/wishbone2asmi: cache hits working
|
2012-02-13 23:11:16 +01:00 |
|
Sebastien Bourdeauducq
|
264be80f2d
|
Fix syntax errors and other stupid problems
|
2012-02-13 22:28:02 +01:00 |
|
Sebastien Bourdeauducq
|
8a61d9d121
|
bus/csr: Rename a->adr d->dat to be consistent with the other buses
|
2012-02-13 21:46:39 +01:00 |
|
Sebastien Bourdeauducq
|
060426cb59
|
bus/wishbone2asmi: set WM, and send 0 when inactive
|
2012-02-13 16:49:43 +01:00 |
|
Sebastien Bourdeauducq
|
cad9d3b960
|
bus: Wishbone to ASMI caching bridge (untested)
|
2012-02-13 16:29:38 +01:00 |
|
Sebastien Bourdeauducq
|
7894411418
|
bus/asmibus: fix typo
|
2012-02-11 20:56:01 +01:00 |
|
Sebastien Bourdeauducq
|
ef436a1ec9
|
bus/asmibus: add get_slots, fix get_fragment
|
2012-02-10 17:49:06 +01:00 |
|
Sebastien Bourdeauducq
|
945d655d45
|
bus: ASMI hub (untested)
|
2012-02-10 15:21:04 +01:00 |
|
Sebastien Bourdeauducq
|
47883675db
|
bus/wishbone2csr: truncate WB data
|
2012-02-06 18:43:34 +01:00 |
|
Sebastien Bourdeauducq
|
a99c2acfa8
|
Remove explicit bus names and rely on the new automatic namer
|
2012-01-27 22:20:57 +01:00 |