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9084 Commits

Author SHA1 Message Date
Maciej Kurc cb8e0193fc Added retransmission logic for EtherBone UDP reads. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-09-20 09:26:24 +02:00
Florent Kermarrec e12af4f050 interconnect/axi/axi_stream: Fix get_ios and base it on length of created Endpoint's signals. 2022-09-20 09:08:22 +02:00
enjoy-digital 23db2e65f4
Merge pull request #1437 from trabucayre/yosys_nextpnr_refactor_args 
build/yosys,nextpnr, lattice: refactor args
 2022-09-19 19:29:34 +02:00
Gwenhael Goavec-Merou e9f6642d8f build/yosys,nextpnr, lattice: refactor args 2022-09-19 19:08:25 +02:00
Florent Kermarrec 32272ba855 axi/axi_stream: Set default keep_width to None and automatically set it to data_width//8 when not specified. 2022-09-19 13:28:42 +02:00
enjoy-digital 860c757f33
Merge pull request #1435 from gsomlo/gls-yosys-flow3 
yosys_nextpnr_toolchain: add flow3 option to abc9 mode
 2022-09-19 09:18:00 +02:00
Gabriel Somlo 441042bef4 yosys_nextpnr_toolchain: add flow3 option to abc9 mode 
Add "flow3" option to abc9 mode. This runs FPGA mapping several times,
producing a generally better mapping at the cost of increased runtime
(see https://github.com/Ravenslofty/yosys-cookbook/blob/master/ecp5.md).

Also, add a "--yosys-flow3" build option to both "trellis" and "oxide".

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2022-09-18 08:28:40 -04:00
Thomas Watson d7837f8751 demo: fix minor build issues 2022-09-17 19:05:45 -05:00
Florent Kermarrec c24bbedb68 interconnect/axi/axi_full: Fix AXIUpConverter compilation. 2022-09-16 14:06:22 +02:00
Florent Kermarrec 1e1e75dba7 software/bios/boot: Fix missing CONFIG_BIOS_NO_DELAYS update. 2022-09-16 14:05:45 +02:00
Florent Kermarrec fa902281aa integration/common/get_mem_data: Allow filemane_or_regions to be None and add endianness assertion. 2022-09-16 14:05:20 +02:00
Florent Kermarrec d36f98bf45 axi/axi_full: Simplify by switching AXI channels to AXIStreamInterface. 2022-09-15 15:52:03 +02:00
Florent Kermarrec bc385c7358 interconnect/axi/axi_stream: Simplify by always adding id/dest/user to endpoints and add layout/name parameters for more flexibility. 2022-09-15 15:25:59 +02:00
Florent Kermarrec 3cd4a3830c cores/dma/WishboneDMAWriter: Add ready_on_idle parameter and set it to 1 by default. 
This allows controlling ready behavior on idle state.
 2022-09-14 10:02:07 +02:00
enjoy-digital 0adb604c97
Merge pull request #1423 from zyp/improve_dma 
Improve DMA
 2022-09-14 09:57:43 +02:00
Dolu1990 89bb688500
Merge pull request #1426 from enjoy-digital/naxriscv-merge 
cpu/NaxRiscv fix peripheral bus width to 32 bits and CLINT is now protected from overflow glitches
 2022-09-12 23:25:47 +02:00
Dolu1990 0a380b9c3b cpu/NaxRiscv improve peripheral read/write speed by staying 32 bits 2022-09-12 19:19:35 +02:00
Dolu1990 8e7fd9bc1f Merge branch 'master' into naxriscv-merge 2022-09-12 19:18:12 +02:00
Florent Kermarrec 23f529a313 soc/builder: Propagate data_width to get_mem_data. 2022-09-12 16:46:20 +02:00
Florent Kermarrec 481234de91 integration/common/get_mem_data: Add data_width support. 2022-09-12 16:45:55 +02:00
Florent Kermarrec a7cc1af416 soc: Propagate main bus address_width to the different interfaces dynamically created. 2022-09-12 16:13:45 +02:00
Florent Kermarrec 95bed6de5c interconnect/wishbone: Allow passing address_width (In byte addressing). 
This is useful to abstract interfaces and propagate address_width.

Idealy, Wishbone should be fully switch to byte addressing since word addressing
has been a source of common issues/errors in the past but compatibility issues
would need to be evaluated first.
 2022-09-12 16:12:52 +02:00
Florent Kermarrec 91c521a22a Changes: Prepare for next release changes. 2022-09-12 11:08:50 +02:00
Florent Kermarrec ded3bad178 cpu/naxriscv: Minor cleanups on recent changes. 2022-09-12 11:01:42 +02:00
Dolu1990 f2a088bfcc
Merge pull request #1355 from cklarhorst/master 
integration/soc Add accessible_region to add_memory_buses
 2022-09-12 10:18:22 +02:00
Florent Kermarrec fa0c2df687 CHANGES: Update and release. 2022-09-12 09:00:36 +02:00
Vegard Storheil Eriksen 3c4c12a72f cores/dma: End transfer when the last flag is set. 2022-09-10 10:15:37 +02:00
Vegard Storheil Eriksen 6ad6d1e414 cores/dma: Don’t drop data while idle. 2022-09-10 10:15:37 +02:00
Christian Klarhorst 6367fc6cab update naxriscv comments 2022-09-09 13:19:36 +02:00
Florent Kermarrec 15f72174ce interconnect/axi/axi_full: Add region signal to aw/ar and optional user signal to aw/w/b/ar/r channels. 2022-09-09 12:46:31 +02:00
Dolu1990 14160ce7e3 cpu/NaxRiscv update nax with peripheral memory region 2022-09-09 11:23:24 +02:00
Florent Kermarrec b7e2d24f37 interconnect/wishbone/DownConverter: Avoid FSM and Idle cycle. 2022-09-08 17:41:24 +02:00
Christian Klarhorst a04f20880f Change naxriscv memory-region format 
It now has a mode and a bus field.
modes: rwxc (read, write, execute, cachable)
bus: pm (peripheral, memory)
 2022-09-08 17:33:20 +02:00
Florent Kermarrec e5de4b356a interconnect/axi/axi_lite: Add prot signal. 
Not directly used by LiteX but useful for wrapping AXI-Lite RTL code.
 2022-09-08 12:06:35 +02:00
Florent Kermarrec 3b714c8145 test: Add minimal test_axi_stream test (Just syntax check for now). 2022-09-08 11:53:05 +02:00
Florent Kermarrec afc89c9350 interconnect/axi/axi_stream: Add ID/Dest support and minor cleanup. 2022-09-08 11:51:55 +02:00
Florent Kermarrec 5b8d3651a9 software/liblitedram: Enable ECP5DDRPHY features on GW2DDRPHY (since very similar). 2022-09-07 16:27:54 +02:00
Florent Kermarrec ee536f9cd5 CONTRIBUTORS: Update. 2022-09-07 10:13:17 +02:00
Florent Kermarrec 85e8aab5ae tools/litex_contributors: Sort contributors by names. 
The git .csv generation is already sorted but this needs to be sorted again due
to the companies renaming.
 2022-09-07 10:07:12 +02:00
Florent Kermarrec 0bd19fd026 tools/litex_contributors: Rename authors to contributors. 2022-09-07 09:49:26 +02:00
Florent Kermarrec 0144612751 tools/litex_contributors: Add RapidSilicon to companies. 
RapidSilicon is helping funding the improvement/development of LiteX features
and the team also contribute directly to the project.
 2022-09-07 09:48:27 +02:00
Florent Kermarrec 4d6813ae64 tools/litex_contributors: Sort years. 2022-09-07 09:42:20 +02:00
Florent Kermarrec a6acfb9a37 stream/Buffer: Integrate PipeValid/PipeReady (both configurable) and add tests. 
Allow selecting pipelining of valid/data or/and ready and creating a full Skid Buffer
(Pipeline of both valid/data and ready).
 2022-09-07 08:59:37 +02:00
Dolu1990 ce90181046 cpu/VexRiscv_SMP add --wishbone-force-32b option 2022-09-06 13:13:45 +02:00
Dolu1990 af43e98e78 Merge branch 'naxriscv-merge' 2022-09-06 13:07:54 +02:00
Dolu1990 5fad94f9d6 cpu/VexRiscv_SMP add --wishbone-force-32b option 2022-09-06 11:23:36 +02:00
Florent Kermarrec 36297c7a1e cores/video: Avoid serializer_attrs. 2022-09-05 09:49:15 +02:00
enjoy-digital 398811b910
Merge pull request #1413 from trabucayre/gowin_HDMI 
soc/cores/video: adding Gowin HDMI Phy
 2022-09-05 09:32:29 +02:00
enjoy-digital 8159b5caad
Merge pull request #1412 from umarcor/umarcor/f4pga 
litex/build/xilinx/f4pga: update imports
 2022-09-02 19:03:02 +02:00
Gwenhael Goavec-Merou a9c7e868e7 soc/cores/video: adding Gowin HDMI Phy 2022-09-02 19:00:33 +02:00