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78 Commits

Author SHA1 Message Date
whitequark 4b6bd43d8e Enable ror, ffl1 and addc for OR1K. 2015-07-30 10:55:01 +03:00
whitequark a4e14f1058 Don't build base libraries and BIOS with -fPIC after all. 2015-07-29 12:09:05 +03:00
Sebastien Bourdeauducq f2eff4d10e soc: increase default BIOS size 2015-07-28 22:36:42 +08:00
whitequark c8ffd0c9ee Switch to -fPIC. 
Using -fPIC for everything allows to link the MiSoC static libraries
both into static images such as the BIOS as well as
into shared libraries.
 2015-07-26 16:06:48 +03:00
Sebastien Bourdeauducq 31a447154d soc: support constants without value 2015-06-28 21:35:37 +02:00
Florent Kermarrec f44956bfca soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined 2015-06-19 08:39:37 +02:00
Sebastien Bourdeauducq 7c2d0fa641 indentation 2015-06-17 08:32:17 -06:00
Florent Kermarrec c0bc94ca1c soc/sdram: add capability to share L2 cache in multi-CPU SoCs 2015-06-17 15:48:45 +02:00
Florent Kermarrec 3b9f287bab sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon 2015-06-17 15:30:30 +02:00
Florent Kermarrec 1bb2580779 sdram: use new Migen Converter in Minicon frontend and small cleanup 2015-06-02 19:37:08 +02:00
Florent Kermarrec f40140dba5 sdram: refactor minicon and fix issues with DDRx memories 
- simplify code
- fix AddressSlicer
- manage write latency and write to precharge timings
- add odt/reset_n signals
 2015-05-29 12:31:56 +02:00
Florent Kermarrec 553262bcc1 soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment... 2015-05-04 12:28:49 +02:00
Florent Kermarrec c98bd9fd79 rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq) 2015-05-02 17:07:58 +02:00
Florent Kermarrec a4617014f4 cores: avoid having too much directories when possible (for simple cores or cores contained in a single file) 2015-05-02 16:22:33 +02:00
Florent Kermarrec 93de581931 soc: add shadow_address parameter 
When don't necessary want to have shadow memories and be able to start CSR at address 0x00000000(for example with an X86 CPU)
 2015-04-17 13:42:29 +02:00
Florent Kermarrec 9666629c4f soc/cpuif: add with_access_functions parameter 
When don't necessary need access functions in our csr.h (for example with an X86 CPU)
 2015-04-17 13:26:38 +02:00
Florent Kermarrec 2ccb5655c9 global: more pep8 
we will have to continue the work... volunteers are welcome :)
 2015-04-13 18:02:26 +02:00
Florent Kermarrec fc68d915c1 global: pep8 (E261, E271) 2015-04-13 17:16:12 +02:00
Florent Kermarrec f3c010c1d5 global: pep8 (E225) 2015-04-13 17:01:05 +02:00
Florent Kermarrec f68423f423 global: pep8 (E302) 2015-04-13 16:47:22 +02:00
Florent Kermarrec d9e09707ae global: pep8 (replace tabs with spaces) 2015-04-13 16:19:55 +02:00
Sebastien Bourdeauducq 3a2b677f85 soc,cpuif: support user defined constants 2015-04-09 00:34:36 +08:00
Sebastien Bourdeauducq 176b9240a9 soc: use new ModuleTransformer API 2015-04-06 23:52:34 +08:00
Florent Kermarrec 2583e975f0 soc/cpuif: fix CSR base generation for memories (name is already fullname) 2015-04-03 13:57:37 +02:00
Florent Kermarrec c9c11e7aa8 soc: add memory.name_override to name when adding csrbankarray.srams to csr_regions 2015-04-03 12:45:32 +02:00
Sebastien Bourdeauducq 85b3cced22 use str.format 2015-04-03 17:43:46 +08:00
Florent Kermarrec 0db6e1d624 soc/cpuif: fix get_csr_header when obj is Memory (thanks ccube) 2015-04-03 11:14:28 +02:00
Sebastien Bourdeauducq 382ed013af minor cleanups 2015-04-02 14:40:29 +08:00
Sebastien Bourdeauducq bbdbf87599 Merge branch 'master' of github.com:m-labs/misoc 2015-04-02 10:14:24 +08:00
Florent Kermarrec 2d23ab7a85 soc/sdram: fix do_finalize 2015-04-01 22:38:04 +02:00
Sebastien Bourdeauducq 2900429e65 soc: use set 2015-04-02 00:14:56 +08:00
Sebastien Bourdeauducq 369086a178 soc: simplify integrated memory parameters 2015-04-02 00:09:38 +08:00
Sebastien Bourdeauducq 273242b399 soc/sdram: minor cleanup 2015-04-01 23:41:55 +08:00
Sebastien Bourdeauducq 9599eb6fae soc: remove cpu_boot_file argument 2015-04-01 17:32:45 +08:00
Sebastien Bourdeauducq fb86445d14 soc: remove cpu_or_bridge and with_cpu arguments 2015-04-01 17:29:51 +08:00
Sebastien Bourdeauducq a148af97ba soc: retrieve csr and memory regions using methods 2015-04-01 16:49:32 +08:00
Sebastien Bourdeauducq 8b19a11cd7 soc: use add_wb_master function 2015-04-01 15:56:54 +08:00
Sebastien Bourdeauducq 2a1112b912 soc: simplify/fix csr busword 2015-04-01 15:48:56 +08:00
Sebastien Bourdeauducq 04f29e97e2 soc: remove unnecessary imports 2015-04-01 15:15:09 +08:00
Sebastien Bourdeauducq 5113301130 soc: improve memory region conflict check 2015-04-01 15:14:02 +08:00
Sebastien Bourdeauducq 980791e2b8 soc: remove ns function 2015-04-01 14:33:12 +08:00
Florent Kermarrec b313772a0c sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0) 2015-03-29 12:34:40 +02:00
Florent Kermarrec be20fbabe4 soc: limit main_ram_size to 256MB (we should modify mem_map to allow larger memories, this was the probably ARTIQ runtime issue....!!) 2015-03-28 23:35:44 +01:00
Florent Kermarrec 0649ded5fd soc: simplify main_ram_size computation and share it between LASMIcon and Minicon 2015-03-28 23:10:33 +01:00
Florent Kermarrec ba8b24df57 sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy 2015-03-25 16:57:38 +01:00
Florent Kermarrec 7ea9e2ba89 sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings. 2015-03-25 16:56:29 +01:00
Florent Kermarrec 30c2521eb0 sdram: pass sdram_controller_settings to SDRAMSoC 2015-03-21 23:12:18 +01:00
Florent Kermarrec 70469e1f37 sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit) 2015-03-21 21:32:39 +01:00
Florent Kermarrec 9bc71f374a rename sdram mapping to main_ram 2015-03-21 21:01:46 +01:00
Florent Kermarrec c55199deb9 misoclib/soc: add _integrated_ to cpu options to avoid confusion 2015-03-21 20:51:37 +01:00