Florent Kermarrec
|
5b34f4cd34
|
soc/add_cpu: use cpu.data_width as CSR alignment, fix regression on Rocket
|
2020-02-12 21:25:52 +01:00 |
Florent Kermarrec
|
2f69f607e3
|
integration/soc: fix refactoring issues
|
2020-02-12 18:16:38 +01:00 |
Florent Kermarrec
|
1d6ce66bf7
|
soc/integration/builder: update copyright, align arguments
|
2020-02-12 16:43:11 +01:00 |
enjoy-digital
|
98ae91ada5
|
Merge pull request #383 from Xiretza/builder-directories
Unify output directory handling in builder
|
2020-02-12 16:38:04 +01:00 |
Xiretza
|
b56545791c
|
Unify output directory handling in builder
|
2020-02-12 15:47:16 +01:00 |
enjoy-digital
|
4a15c3e219
|
Merge pull request #382 from enjoy-digital/new_soc
Add new SoC/LiteXSoC classes and use it for SoCCore/SoCSDRAM
|
2020-02-11 18:39:33 +01:00 |
Florent Kermarrec
|
e9c665a539
|
soc_core/soc_sdram: add disclaimer
|
2020-02-11 18:28:05 +01:00 |
Florent Kermarrec
|
5558865cbf
|
soc_core: provide full retro-compatibily when add_wb_slave is called before add_memory_region
|
2020-02-11 18:21:41 +01:00 |
Florent Kermarrec
|
1b5caf56fb
|
soc: fix busword typo
|
2020-02-11 17:57:05 +01:00 |
Florent Kermarrec
|
8b5cc34553
|
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
|
2020-02-11 17:44:24 +01:00 |
enjoy-digital
|
240a55bace
|
Merge branch 'master' into new_soc
|
2020-02-11 17:22:06 +01:00 |
Florent Kermarrec
|
d5ad1d56f2
|
soc/integration: move mem_decoder to soc_core
|
2020-02-11 17:19:22 +01:00 |
Florent Kermarrec
|
0a737cb624
|
soc/integration/common: simplify get_version
|
2020-02-11 17:16:24 +01:00 |
Florent Kermarrec
|
399b65fa17
|
soc/add_uart: fix bridge
|
2020-02-11 16:55:37 +01:00 |
Florent Kermarrec
|
160c55d1d4
|
soc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted)
|
2020-02-11 16:44:25 +01:00 |
Florent Kermarrec
|
b2c66b1efd
|
soc: avoid double definition of main_ram
|
2020-02-11 16:39:37 +01:00 |
Florent Kermarrec
|
5f9946085b
|
soc: improve log colors on error reporting
|
2020-02-11 16:24:57 +01:00 |
Florent Kermarrec
|
b22d2ca02b
|
soc: add linker regions management
|
2020-02-11 15:28:02 +01:00 |
Florent Kermarrec
|
abc31a92c6
|
soc: improve log presentation/colors
|
2020-02-11 14:50:16 +01:00 |
Florent Kermarrec
|
91e2797bb4
|
soc: fix cpu_reset_address
|
2020-02-11 14:17:32 +01:00 |
Florent Kermarrec
|
0d7430fc69
|
tools/litex_sim_new: remove
|
2020-02-11 14:05:01 +01:00 |
Florent Kermarrec
|
21d38701df
|
soc: fix build_time format
|
2020-02-11 13:23:53 +01:00 |
Florent Kermarrec
|
4d761e1afd
|
cores/cpu: remove separators on io_regions (requires python 3.6)
|
2020-02-11 13:12:54 +01:00 |
enjoy-digital
|
7c57a33ba0
|
Merge pull request #380 from Xiretza/cpunone-all-io
Allow all memory regions to be used as IO with CPUNone
|
2020-02-11 13:11:33 +01:00 |
Florent Kermarrec
|
b43d830fda
|
soc/add_sdram: simplify L2 Cache, use FullMemoryWE on L2 Cache by default (seems better on all devices)
|
2020-02-11 09:30:45 +01:00 |
Florent Kermarrec
|
ea8e745ac2
|
soc_core/common: move old mem_decoder to soc_core, simplify get_version
|
2020-02-11 08:44:23 +01:00 |
Xiretza
|
e301df7f56
|
Allow all memory regions to be used as IO with CPUNone
|
2020-02-10 19:56:36 +01:00 |
Florent Kermarrec
|
16d1972bf8
|
integration/common: fix mem_decoder (shadow base has been deprecated)
|
2020-02-10 19:40:56 +01:00 |
Florent Kermarrec
|
5e11e8391f
|
tools/litex_sim_new: switch to dynamically allocated ethmac origin
|
2020-02-10 19:37:53 +01:00 |
Florent Kermarrec
|
dd0c71d7a1
|
soc/SoCRegion/Decoder: pass bus to decoder and remove mask on origin
|
2020-02-10 19:34:18 +01:00 |
Florent Kermarrec
|
e8e4537e14
|
soc/add_sdram: avoid L2 cache when l2_cache_size == 0.
|
2020-02-10 19:02:44 +01:00 |
Florent Kermarrec
|
dcbdb73231
|
soc: remove unneeded \n
|
2020-02-10 18:38:59 +01:00 |
Florent Kermarrec
|
0f1811fb51
|
tools/litex_sim_new: use new bus/csr/irq methods
|
2020-02-10 18:21:41 +01:00 |
Florent Kermarrec
|
d320be8ecb
|
soc: use io_regions for alloc_region
|
2020-02-10 18:19:35 +01:00 |
Florent Kermarrec
|
9ac09ddde5
|
tools: add litex_sim_new based on SoCCore and using add_sdram method
|
2020-02-10 18:00:46 +01:00 |
Florent Kermarrec
|
cbcd953dd7
|
soc_core: use add_rom
|
2020-02-10 17:43:29 +01:00 |
Florent Kermarrec
|
487ac3da9a
|
soc/add_cpu: simplify CPUNone integration
|
2020-02-10 17:40:46 +01:00 |
Florent Kermarrec
|
f7d4648ca1
|
soc/SoCBusHandler: add add_adapter method and use it to convert Master/Slave before connecting to the Bus
|
2020-02-10 17:17:31 +01:00 |
Florent Kermarrec
|
379d47a843
|
soc/add_sdram: add sdram csr
|
2020-02-10 17:02:20 +01:00 |
Florent Kermarrec
|
3921b6345c
|
soc/add_sdram: fix rocket, shorten comments
|
2020-02-10 16:55:15 +01:00 |
Florent Kermarrec
|
14b627b466
|
soc/add_sdram: improve API
|
2020-02-10 16:38:20 +01:00 |
Florent Kermarrec
|
1faefdc0fa
|
soc: add LiteXSoC class and mode add_identifier/uart/sdram to it
|
2020-02-10 16:28:11 +01:00 |
Florent Kermarrec
|
11dbe19084
|
soc_core/sdram: cleanup, add disclaimer
|
2020-02-10 16:21:21 +01:00 |
Florent Kermarrec
|
5eb88cd904
|
soc: add add_sdram
|
2020-02-10 16:01:19 +01:00 |
Florent Kermarrec
|
39011593ac
|
soc: add csr_regions, update copyright
|
2020-02-10 15:11:37 +01:00 |
Florent Kermarrec
|
d2b069516a
|
soc: add cpu rom/sram check
|
2020-02-10 14:48:46 +01:00 |
Florent Kermarrec
|
de100fddf5
|
soc: add SOCIORegion and manage it
|
2020-02-10 14:36:53 +01:00 |
Florent Kermarrec
|
6b8c425f9b
|
soc: reorder main components/peripherals
|
2020-02-10 13:07:09 +01:00 |
Florent Kermarrec
|
84b5df7871
|
soc: add add_cpu method
|
2020-02-09 21:56:32 +01:00 |
Florent Kermarrec
|
7ee9ce38a7
|
.gitmodules/black-parrot: switch to https://github.com/enjoy-digital/black-parrot (without the submodules)
|
2020-02-09 19:53:04 +01:00 |