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Author SHA1 Message Date
Florent Kermarrec
cef2369015 core/spi_flash: re-integrate bitbang write support 2019-06-25 19:09:30 +02:00
Mateusz Holenko
2ee194b259 bios: add fw (flash write) command 2019-06-25 16:58:12 +02:00
Florent Kermarrec
5cc4c334d6 README: remove LiteUSB (deprecated) 2019-06-24 15:41:22 +02:00
Florent Kermarrec
dc03b7fab9 boards: community supported boards are now located at https://github.com/litex-hub/litex-boards 2019-06-24 12:05:02 +02:00
Florent Kermarrec
0af017e67c liteeth: update mac imports (olds still works, but that's now the prefered way) 2019-06-24 11:45:01 +02:00
Florent Kermarrec
ecf999b8c7 soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB 
LiteUSB was not up to date was not a real USB PHY but was just providing USB FIFO PHYs.
New true USB cores are now available: Daisho, ValentyUSB, so it's better using
then for true USB support. We only keep the FT245 FIFO PHY in LiteX that can be
useful to interface with USB2/USB3 USB FIFOs.
 2019-06-24 10:58:36 +02:00
Florent Kermarrec
e667d5ae53 README: update Intro 2019-06-24 09:59:10 +02:00
Florent Kermarrec
8f6e66ca52 make sure #!/usr/bin/env python3 is before copyright header 2019-06-24 07:29:24 +02:00
Florent Kermarrec
c7f36ab08f test: add copyright header 2019-06-23 23:31:11 +02:00
Florent Kermarrec
daa4307d9e add CONTRIBUTORS file and add copyright header to all files 2019-06-23 23:23:56 +02:00
Florent Kermarrec
361f9d0dff bios/sdram: set init_done/error when DDRCTRL is present (litedram_gen) 2019-06-22 10:55:15 +02:00
Tim 'mithro' Ansell
d8ac936206 Convert top level comment to a docstring. 2019-06-21 12:03:30 -07:00
enjoy-digital
45632c66b1
Merge pull request #202 from xobs/add-up5kspram 
soc: cores: add up5kspram module
 2019-06-21 10:26:07 +02:00
William D. Jones
7656f54d0a soc: cores: add up5kspram module 
The ICE40UP5K has 128 kB of SPRAM that's designed to be used
as memory for a softcore.  This memory is actually 4 16-bit
chunks that we can gang together to give us either 64 kB or
128 kB.

Add a module that will allow us to use this memory in an ICE40.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-20 11:12:46 -07:00
Florent Kermarrec
73dbffe8f2 cores/frequency_meter: allow passing clk to be measured as a parameter 2019-06-20 09:03:30 +02:00
enjoy-digital
408d3f1f7c
Merge pull request #201 from gsomlo/gls-fix-initmem 
tools/litex_sim: fix default endianness for mem_init
 2019-06-19 08:32:38 +02:00
Gabriel L. Somlo
ab827d210d tools/litex_sim: fix default endianness for mem_init 
Initializing ROM and/or RAM content requires knowing the CPU
endianness before the SimSoC->SoCSDRAM->SoCCore constructor
sequence is invoked (before the SoC's self.cpu.endianness
could be accessed). Given that the majority of supported CPU
models use "little", set it as the new default, and override
only for the two models that use "big" endianness.
 2019-06-18 16:55:58 -04:00
enjoy-digital
f47b4902e5
Merge pull request #200 from gsomlo/gls-rocket-variants 
cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants
 2019-06-18 13:15:30 +02:00
Gabriel L. Somlo
f75863fc31 cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants 2019-06-18 06:46:24 -04:00
Florent Kermarrec
c0df9e0823 cpu/rocket: update submodule 2019-06-18 09:44:13 +02:00
Florent Kermarrec
87118d509c integration/soc_core: move cpu_variant checks/formating to cpu 2019-06-17 09:55:27 +02:00
Florent Kermarrec
f6b67a6dae cpu/vexriscv: add "linux+no-dsp" variant 2019-06-17 09:54:17 +02:00
Florent Kermarrec
95b1b454f4 cpu/vexriscv: update 2019-06-17 09:24:57 +02:00
Florent Kermarrec
e46d287b64 targets/ulx3s: use CAS latency of 3 to be compatible with production boards 2019-06-17 09:20:21 +02:00
enjoy-digital
113f7f408e
Merge pull request #199 from ambrop72/no-ethmac-fix 
bios: Fix build when ethphy is present but ethmac is not.
 2019-06-13 07:14:03 +02:00
Ambroz Bizjak
ca70ea91e4
bios: Fix build when ethphy is present but ethmac is not. 
While testing my Ethernet DMA, I renamed the `ethmac` module to `ethmac_dma` so that it wouldn't be used from the BIOS, but I got an undefined reference to `eth_init` because `bios.c` checks different CSR defines than the code that defines `eth_init`.
 2019-06-13 01:02:22 +02:00
Florent Kermarrec
ab1f580470 test/test_axi: remove litex.gen.sim import (was only useful for debug) 2019-06-12 11:28:06 +02:00
Florent Kermarrec
5318bcd3c3 setup.py: add migen to install_requires 2019-06-12 11:26:57 +02:00
enjoy-digital
33d7cc5fc8
Merge pull request #198 from TomKeddie/tomk_20190610_artyspi 
boards/arty : Add directly connected spi clk pin
 2019-06-11 15:50:02 +02:00
Florent Kermarrec
38a2d89a25 test/test_code8b10b: add test_coding 2019-06-10 18:53:30 +02:00
Tom Keddie
5346c3684f boards/arty : Add directly connected spi clk pin to avoid need for STARTUPE2 2019-06-10 08:33:02 -07:00
Florent Kermarrec
8fdd5220b3 test/test_prbs: add PRBSGenerator/Checker tests 2019-06-10 16:19:23 +02:00
Florent Kermarrec
243d7c7696 soc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker 
Imported from LiteICLink. PRBS can be useful for different purposes, so is
better integrated in LiteX.
 2019-06-10 16:05:36 +02:00
Florent Kermarrec
cfa952b062 tools/litex_term: exit on 2 consecutive CTRL-C 
When running OS with LiteX and when LiteXTerm is use, we want to be able to
send CTRl-C to the OS. Ensure a specific sequence is sent to close the terminal.
 2019-06-10 15:06:57 +02:00
Florent Kermarrec
1c34b4a015 cpu/vexriscv: update submodule 2019-06-10 12:57:21 +02:00
Florent Kermarrec
79665873df doc: add litex-hub logo 2019-06-09 19:36:09 +02:00
Florent Kermarrec
442d7358ce doc: redesign new logo 2019-06-09 00:36:46 +02:00
Florent Kermarrec
591186279a doc: add new logo 2019-06-08 00:45:30 +02:00
Florent Kermarrec
850b311d04 cpu/vexriscv: update submodule 2019-06-07 18:36:46 +02:00
Florent Kermarrec
755a2660ba build/sim: allow configuring verilator optimization level 2019-06-07 12:28:20 +02:00
Florent Kermarrec
4b6ad8aa0d build/sim: allow defining start/end cycles for tracing 2019-06-07 11:50:57 +02:00
Florent Kermarrec
ecb60f6e43 build/sim: use -O0 for verilator compilation 
In most of the case, execution speed is already fast enough with -O0 and
with complex design -O0 is a lost faster to compile than -O3. In the future
we could add a switch to choose which optimization we want.
 2019-06-07 11:16:39 +02:00
Florent Kermarrec
c64129dc69 soc/integration/soc_core: list rocket as supported CPU 2019-06-07 11:14:36 +02:00
Florent Kermarrec
ca4e7811e9 software/bios: change prompt to "litex" in green. 2019-06-07 11:13:36 +02:00
Florent Kermarrec
8d0f008a3b integration/soc_core: improve readibility (add separators/comments) 2019-06-05 23:43:16 +02:00
Florent Kermarrec
55ebcc00eb test/test_targets: add de10lite 2019-06-05 20:03:19 +02:00
enjoy-digital
e545b15f66
Merge pull request #196 from msloniewski/de10lite_support 
De10lite support
 2019-06-05 19:44:54 +02:00
enjoy-digital
77805a5e26
Merge pull request #195 from antmicro/extend_generated_headers 
Extend generated headers & csv
 2019-06-05 19:20:15 +02:00
msloniewski
04ce479035 boards/targets: add target for de10lite platform 2019-06-05 18:57:59 +02:00
msloniewski
f2a740d51d boards/platforms: add de10lite Terasic platform support 2019-06-05 18:57:59 +02:00