Sebastien Bourdeauducq
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574becc1fc
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fhdl/specials: clean up clock domain handling
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2013-03-26 11:58:34 +01:00 |
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Sebastien Bourdeauducq
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17f2b17654
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fhdl/verilog: optionally disable clock domain creation
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2013-03-18 18:45:19 +01:00 |
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Sebastien Bourdeauducq
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7a06e9457c
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Lowering of Special expressions + support ClockSignal/ResetSignal
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2013-03-18 18:36:50 +01:00 |
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Sebastien Bourdeauducq
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bd8bbd9305
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Make ClockDomains part of fragments
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2013-03-15 18:17:33 +01:00 |
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Sebastien Bourdeauducq
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ecfe1646ec
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fhdl/verilog: implicit get_fragment
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2013-03-12 16:16:06 +01:00 |
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Sebastien Bourdeauducq
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6fa30053bf
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fhdl/verilog: tristate outputs are always wire
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2013-03-06 11:30:52 +01:00 |
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Sebastien Bourdeauducq
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c10622f5e2
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fhdl/verilog: insert reset before listing signals
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2013-02-27 18:10:04 +01:00 |
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Sebastien Bourdeauducq
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7c4e6c35e5
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fhdl/verilog: support special lowering and overrides
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2013-02-23 19:03:16 +01:00 |
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Sebastien Bourdeauducq
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49cfba50fa
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New 'specials' API
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2013-02-22 17:56:35 +01:00 |
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Sebastien Bourdeauducq
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dc93a231c6
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fhdl: tristate support
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2013-02-15 00:17:24 +01:00 |
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Sebastien Bourdeauducq
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3201554f76
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fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
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2013-01-23 15:13:06 +01:00 |
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Sebastien Bourdeauducq
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badba89686
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fhdl: support nested statement lists
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2013-01-05 14:18:15 +01:00 |
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Sebastien Bourdeauducq
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70e97e0456
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Fix various errors from new bitwidth/signedness system conversion
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2012-11-29 23:36:55 +01:00 |
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Sebastien Bourdeauducq
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261166d92b
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fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
|
2012-11-29 22:59:54 +01:00 |
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Sebastien Bourdeauducq
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50ed73c937
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New specification for width and signedness
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2012-11-29 21:22:38 +01:00 |
|
Sebastien Bourdeauducq
|
6eebfce44a
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Refactor Case
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2012-11-29 01:11:15 +01:00 |
|
Sebastien Bourdeauducq
|
fee22a4631
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Remove Constant
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2012-11-28 23:18:43 +01:00 |
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Sebastien Bourdeauducq
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9d3e218863
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fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.
|
2012-11-23 18:38:03 +01:00 |
|
Sebastien Bourdeauducq
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51e2e6ecd0
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fhdl/verilog: remove empty cases
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2012-11-18 16:32:51 +01:00 |
|
Sebastien Bourdeauducq
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c273866b08
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fhdl: support expressions in instance ports
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2012-09-22 20:51:10 +02:00 |
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Sebastien Bourdeauducq
|
2fc9cae88a
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fhdl: support inverted clock ports in instances
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2012-09-22 20:50:49 +02:00 |
|
Sebastien Bourdeauducq
|
2e14569b5c
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fhdl/verilog: sort clock domains by name
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2012-09-11 10:00:03 +02:00 |
|
Sebastien Bourdeauducq
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9a18a9df3f
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fhdl: list signals in execution order
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2012-09-11 09:59:37 +02:00 |
|
Sebastien Bourdeauducq
|
e16353a281
|
Multi-clock design support + new instance API
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2012-09-10 23:45:02 +02:00 |
|
Sebastien Bourdeauducq
|
8de192dfbd
|
x.bv.width -> len(x)
|
2012-07-13 18:32:54 +02:00 |
|
Sebastien Bourdeauducq
|
7f47a2568a
|
fhdl: remove _StatementList
|
2012-07-13 17:07:56 +02:00 |
|
Sebastien Bourdeauducq
|
ed27783a53
|
fhdl: arrays (TODO: use correct BV for intermediate signals)
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2012-07-09 15:16:38 +02:00 |
|
Sebastien Bourdeauducq
|
398ece8fe2
|
fhdl/verilog: add option to display which comb blocks are run
This is a debug hack to help find combinatorial loops in designs.
|
2012-04-30 16:38:40 -05:00 |
|
Sebastien Bourdeauducq
|
2a4e49e381
|
fhdl: phase out pads
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2012-04-02 19:21:43 +02:00 |
|
Sebastien Bourdeauducq
|
623e8e436a
|
fhdl/verilog: do not attempt to initialize instance and mem output signals
|
2012-04-02 12:59:42 +02:00 |
|
Sebastien Bourdeauducq
|
f3ae22f488
|
fhdl/verilog: initialize internal read-only signals with their reset values
|
2012-04-01 16:39:11 +02:00 |
|
Sebastien Bourdeauducq
|
90184b22d2
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fhdl/verilog: fix signed constant conversion
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2012-03-06 16:45:44 +01:00 |
|
Sebastien Bourdeauducq
|
a1ad30faab
|
fhdl/verilog: properly connect instance inouts
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2012-02-17 11:08:41 +01:00 |
|
Sebastien Bourdeauducq
|
ca7056b07f
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fhdl: support forwarding of bidirectional signals from instance ports
|
2012-02-16 18:34:32 +01:00 |
|
Sebastien Bourdeauducq
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1eb348c573
|
fhdl: do not attempt slicing non-array signals to keep Verilog happy
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2012-02-06 18:07:02 +01:00 |
|
Sebastien Bourdeauducq
|
5405a83ff9
|
fhdl: memories working
|
2012-01-27 20:22:17 +01:00 |
|
Sebastien Bourdeauducq
|
a5bd111370
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fhdl/verilog: clean up signal classification and support memory descriptions
|
2012-01-27 16:54:48 +01:00 |
|
Sebastien Bourdeauducq
|
d3d5b481fe
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Include fragment pads in pre-naming dictionary
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2012-01-20 22:59:40 +01:00 |
|
Sebastien Bourdeauducq
|
e9be3241f6
|
Fix instance support
|
2012-01-20 22:36:17 +01:00 |
|
Sebastien Bourdeauducq
|
e4f531a739
|
Include unused I/Os in pre-naming dictionary and register signals with name_override
|
2012-01-20 22:20:32 +01:00 |
|
Sebastien Bourdeauducq
|
4eac60d181
|
New naming system: second attempt
|
2012-01-19 18:25:25 +01:00 |
|
Sebastien Bourdeauducq
|
bdde97f5fd
|
New naming system beginning to work
|
2012-01-16 18:42:55 +01:00 |
|
Sebastien Bourdeauducq
|
ab8e08a2ed
|
fhdl: new naming system (broken)
|
2012-01-16 18:09:52 +01:00 |
|
Sebastien Bourdeauducq
|
aa8b8da684
|
fhdl: allow None statements
|
2012-01-15 17:45:54 +01:00 |
|
Sebastien Bourdeauducq
|
7b395b565e
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verilog: split comb block, use assign statements
|
2012-01-07 12:19:06 +01:00 |
|
Sebastien Bourdeauducq
|
f209bf6b33
|
convtools -> tools
|
2012-01-07 00:39:28 +01:00 |
|
Sebastien Bourdeauducq
|
9366a226bb
|
Convert -> convert
|
2012-01-05 19:27:33 +01:00 |
|
Sebastien Bourdeauducq
|
8a394f9159
|
verilog: comb reset
|
2011-12-22 00:04:53 +01:00 |
|
Sebastien Bourdeauducq
|
4d6be55e9f
|
verilog: break down Convert function
|
2011-12-21 23:08:50 +01:00 |
|
Sebastien Bourdeauducq
|
26e0b817e8
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verilog: ignore variable property in combinatorial block
|
2011-12-21 23:00:36 +01:00 |