fea73d932e
soc/cores/clock/intel: speed up PLL config computation
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Caching the list of clock divisors to test speeds up computation by
about a factor of three.
2022-10-01 13:08:16 -05:00
b7ef989963
soc/cores/clock/intel_*: respect PFD input frequency
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Only use input clock divisors which respect the device limitation for
the phase-frequency detector's input frequency. This avoids errors where
Quartus complains the PLL parameters are invalid and refuses to
implement it.
The supported PFD frequencies in integer mode have been verified against
each family's datasheet. The unsupported-by-LiteX fractional frequency
information is removed for clarity.
As a bonus, this speeds up PLL config computation by several times.
2022-10-01 13:00:24 -05:00
d89d6dfd0a
soc/cores/clock/intel_common: cleanup
2022-10-01 12:28:32 -05:00
d531a07719
build/altera: fix clock constraints
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This fixes two issues that prevented clock constraints (e.g.
"add_false_path_constraint") from working properly in Quartus.
The first fix passes the "keep" synthesis attribute through to the
generated Verilog in a way Quartus can understand.
The second fix tells Quartus to name PLL clocks according to their net
instead of the physical pin name by passing the "use_net_name" flag to
"derive_pll_clocks" in the .sdc file. Combined with the above, PLL
clocks will now be named according to the kept net.
This fix has been verified on Quartus Prime Lite 20.1.1.720.
2022-09-30 23:33:52 -05:00
3836e8a36c
Merge pull request #1447 from enjoy-digital/naxriscv-merge
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cpu/naxriscv reduce memory latency on peripheral accesses
2022-09-30 16:21:23 +02:00
43699f2768
interconnect/axi/axi_common: Add missing param signals from connect_to_pads.
2022-09-30 14:36:46 +02:00
c9f669d4ec
Merge branch 'master' into naxriscv-merge
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# Conflicts:
# litex/soc/cores/cpu/naxriscv/core.py
2022-09-30 13:37:03 +02:00
79392e6eb8
soc/cores/jtag/Efinix: Cosmetic cleanups and rename EFINIX_JTAG to EfinixJTAG.
2022-09-30 13:34:00 +02:00
b5b820b27f
Merge pull request #1446 from enjoy-digital/vexriscv-smp-merge
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Add Efinix JTAG support, with vexriscv-smp binding function
2022-09-30 13:17:13 +02:00
622a35fd4e
Improve naxriscv peripheral latency
2022-09-30 11:52:14 +02:00
cb0e9c23d3
Add Efinix JTAG support, with vexriscv-smp binding function
2022-09-30 11:48:07 +02:00
af58237203
software/demo: Add comments for Nix specific changes (To ease future maintenance and avoid breaking it).
2022-09-29 17:30:09 +02:00
1fb1cf19e5
Merge pull request #1434 from tpwrules/fix-bare-metal-demo
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demo: fix minor build issues
2022-09-29 17:20:12 +02:00
c5eaac9c3e
build/xilinx/vivado: Cosmetic cleanup.
2022-09-29 17:16:16 +02:00
28fb3962df
Merge pull request #1444 from cklarhorst/more_vivado_options
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Vivado: Make directives configurable via argparser
2022-09-29 17:12:44 +02:00
ad8b7da63d
Merge pull request #1442 from trabucayre/video_swap_blue_red
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soc/cores/video: swap red and blue channel
2022-09-29 17:04:09 +02:00
8ffdc535d1
Vivado: Make directives configurable via argparser + add option to limit vivado threads
2022-09-29 15:42:15 +02:00
dc0a4ea40b
soc/cores/video: swap red and blue channel
2022-09-27 08:07:31 +02:00
c717e4c824
Merge pull request #1440 from cklarhorst/naxriscv
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Naxriscv: Add two more argparser options for devs
2022-09-26 12:48:47 +02:00
9c43fe85c6
cpu/naxriscv: Add --no-netlist-cache
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Ignores the netlist cache.
When you hack on naxriscv code, you always want fresh results.
2022-09-25 21:00:03 +02:00
7795fba3cf
cpu/naxriscv: Add --update-repo option & check for update errors
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Allows different update strategies which I find useful.
The git update process now checks the return code! So that problems in the update process can be noticed.
2022-09-25 20:51:37 +02:00
759530f272
build/generic_platform, generic_toolchain, yosys_nextpnr_wrapper: introduce the information about ability to do synthesis with mixed languages
2022-09-23 19:02:48 +02:00
b8e22fcd79
interconnect/axi: Simplify/Fix IOs generation. (Param signals were missing for AXIFull).
2022-09-22 09:54:58 +02:00
162a0a4c1e
cpu/rocket: fix variant typos
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The `fulld` and `fullq` variants point to the wrong (`LitexFullConfig`)
verilog. Fix by pointing to the correct code (`LitexFullDConfig` and
`LitexFullQConfig`, respectively).
Reported-by: Ioannis Ioannou <roryt@roryt.gr>
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2022-09-20 09:29:46 -04:00
cb8e0193fc
Added retransmission logic for EtherBone UDP reads.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-09-20 09:26:24 +02:00
e12af4f050
interconnect/axi/axi_stream: Fix get_ios and base it on length of created Endpoint's signals.
2022-09-20 09:08:22 +02:00
23db2e65f4
Merge pull request #1437 from trabucayre/yosys_nextpnr_refactor_args
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build/yosys,nextpnr, lattice: refactor args
2022-09-19 19:29:34 +02:00
e9f6642d8f
build/yosys,nextpnr, lattice: refactor args
2022-09-19 19:08:25 +02:00
32272ba855
axi/axi_stream: Set default keep_width to None and automatically set it to data_width//8 when not specified.
2022-09-19 13:28:42 +02:00
860c757f33
Merge pull request #1435 from gsomlo/gls-yosys-flow3
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yosys_nextpnr_toolchain: add flow3 option to abc9 mode
2022-09-19 09:18:00 +02:00
441042bef4
yosys_nextpnr_toolchain: add flow3 option to abc9 mode
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Add "flow3" option to abc9 mode. This runs FPGA mapping several times,
producing a generally better mapping at the cost of increased runtime
(see https://github.com/Ravenslofty/yosys-cookbook/blob/master/ecp5.md ).
Also, add a "--yosys-flow3" build option to both "trellis" and "oxide".
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2022-09-18 08:28:40 -04:00
d7837f8751
demo: fix minor build issues
2022-09-17 19:05:45 -05:00
c24bbedb68
interconnect/axi/axi_full: Fix AXIUpConverter compilation.
2022-09-16 14:06:22 +02:00
1e1e75dba7
software/bios/boot: Fix missing CONFIG_BIOS_NO_DELAYS update.
2022-09-16 14:05:45 +02:00
fa902281aa
integration/common/get_mem_data: Allow filemane_or_regions to be None and add endianness assertion.
2022-09-16 14:05:20 +02:00
d36f98bf45
axi/axi_full: Simplify by switching AXI channels to AXIStreamInterface.
2022-09-15 15:52:03 +02:00
bc385c7358
interconnect/axi/axi_stream: Simplify by always adding id/dest/user to endpoints and add layout/name parameters for more flexibility.
2022-09-15 15:25:59 +02:00
3cd4a3830c
cores/dma/WishboneDMAWriter: Add ready_on_idle parameter and set it to 1 by default.
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This allows controlling ready behavior on idle state.
2022-09-14 10:02:07 +02:00
0adb604c97
Merge pull request #1423 from zyp/improve_dma
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Improve DMA
2022-09-14 09:57:43 +02:00
89bb688500
Merge pull request #1426 from enjoy-digital/naxriscv-merge
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cpu/NaxRiscv fix peripheral bus width to 32 bits and CLINT is now protected from overflow glitches
2022-09-12 23:25:47 +02:00
0a380b9c3b
cpu/NaxRiscv improve peripheral read/write speed by staying 32 bits
2022-09-12 19:19:35 +02:00
8e7fd9bc1f
Merge branch 'master' into naxriscv-merge
2022-09-12 19:18:12 +02:00
23f529a313
soc/builder: Propagate data_width to get_mem_data.
2022-09-12 16:46:20 +02:00
481234de91
integration/common/get_mem_data: Add data_width support.
2022-09-12 16:45:55 +02:00
a7cc1af416
soc: Propagate main bus address_width to the different interfaces dynamically created.
2022-09-12 16:13:45 +02:00
95bed6de5c
interconnect/wishbone: Allow passing address_width (In byte addressing).
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This is useful to abstract interfaces and propagate address_width.
Idealy, Wishbone should be fully switch to byte addressing since word addressing
has been a source of common issues/errors in the past but compatibility issues
would need to be evaluated first.
2022-09-12 16:12:52 +02:00
91c521a22a
Changes: Prepare for next release changes.
2022-09-12 11:08:50 +02:00
ded3bad178
cpu/naxriscv: Minor cleanups on recent changes.
2022-09-12 11:01:42 +02:00
f2a088bfcc
Merge pull request #1355 from cklarhorst/master
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integration/soc Add accessible_region to add_memory_buses
2022-09-12 10:18:22 +02:00
fa0c2df687
CHANGES: Update and release.
2022-09-12 09:00:36 +02:00
Thomas Watson
Dolu1990
Florent Kermarrec
Christian Klarhorst
Gwenhael Goavec-Merou
Gabriel Somlo
Maciej Kurc