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7676 Commits

Author SHA1 Message Date
Florent Kermarrec 7ed448cd52 cores/bitbang: Attach I2C init table directly to I2C cores and avoid global add_i2c_init_table SoC method. 2022-02-02 10:57:50 +01:00
enjoy-digital 732529ecdf
Merge pull request #1193 from fjullien/i2c_master_init_values 
i2c: automatic device init by the BIOS
 2022-02-02 09:59:31 +01:00
Franck Jullien 7a714c74af i2c: automatic device init by the BIOS 
The BIOS can now initialize I2C peripherals during the boot.
The add_i2c_init_table method of the soc speficy parameters:

self.submodules.i2c = I2CMaster(pads)
self.add_i2c_init_table("i2c", i2c_addr=0x4c, table=it6263_i2c_hdmi_tx)

it6263_i2c_hdmi_tx = [
  (0x05, 0x40),
  (0x04, 0x3D),
  (0x04, 0x1D)
  ...

The table is a list of tupple as (address, value).
 2022-02-01 21:22:51 +01:00
Florent Kermarrec 78ecf50ad5 cores/jtag: Make primitive selection more flexible (and simplify new devices support). 2022-02-01 12:44:18 +01:00
Florent Kermarrec b59fdae588 cores/jtag: Simplify/Cleanup. 2022-02-01 11:32:04 +01:00
Florent Kermarrec 1c5d91dce1 cores/jtag: Deprecate JTAG Atlantic support (Advantageously replaced by JTAG-UART). 2022-02-01 11:19:36 +01:00
Florent Kermarrec 6f6a10db5c CHANGES: Update. 2022-01-31 17:00:51 +01:00
enjoy-digital 0711998dab
Merge pull request #1191 from david-sawatzke/dev/doc_atomic_writes 
Fix generation of documentation of `atomic_write` CSRStorage
 2022-01-31 16:48:02 +01:00
Florent Kermarrec 52a0497032 altera/jtag: Minor cosmetic cleanups, avoid some duplications. 2022-01-31 16:08:08 +01:00
Florent Kermarrec b2448ba50e soc/cores/jtag: Review/Cleanup JTAGTAPFSM and avoid specific CorrectedOngoingResetFSM. 2022-01-31 16:07:50 +01:00
enjoy-digital 40799332a0
Merge pull request #1188 from jevinskie/jev/altera-jtag 
Add JTAGbone support for Altera Max 10 and Cyclone 10 LP
 2022-01-31 16:07:30 +01:00
David Sawatzke a981f935f2 Fix generation of documentation of `atomic_write` CSRStorage 
Can't decrement a range by 1, this (probably) never worked.

Also improves the generated text.
 2022-01-30 18:05:52 +01:00
Jevin Sweval 349087a8c0 Add JTAGbone support for Altera Max 10 and Cyclone 10 LP 2022-01-29 13:27:53 -08:00
Florent Kermarrec bfad61cd2a build/builder: Simplify/Review #1190. 
- Only do copy in Builder.
- Use relative path for copied files (will be useful to create self-contained gateware archive).
 2022-01-28 19:32:12 +01:00
enjoy-digital 3dcc6180f3
Merge pull request #1190 from fjullien/copy_files 
Copy files
 2022-01-28 19:11:40 +01:00
Florent Kermarrec 4de54387d3 soc: Replace remaining add_wb_master call by self.bus.add_master. 2022-01-28 18:41:52 +01:00
Florent Kermarrec 162231fb8f cores/prbs: Define PRBS_CONFIG constants and use them in code. Also simplify PRBSGenerator data selection. 2022-01-28 11:29:47 +01:00
Franck Jullien 598d678f59 Add an argument to add_source for files copy 
With this argument, added files will be copied to the gateware
directory and referenced in the project from this new location.
 2022-01-28 09:53:06 +01:00
Franck Jullien 5fd7c758a1 efinity: don't add unknown language files to sources 2022-01-27 23:14:46 +01:00
enjoy-digital ccd3ab17be
Merge pull request #1187 from fjullien/efinix_fix 
efinix: fix pull up/down constraint
 2022-01-27 20:08:12 +01:00
enjoy-digital 4696e39560
Merge pull request #1186 from trabucayre/xilinx_symbiflow_zynq 
litex/build/xilinx/symbiflow: adding zynq (010 & 020) support
 2022-01-27 20:07:36 +01:00
Franck Jullien b134fcc9c0 efinix: fix pull up/down constraint 2022-01-27 17:11:38 +01:00
Gwenhael Goavec-Merou 21ff32f800 litex/build/xilinx/symbiflow: adding zynq (010 & 020) support 2022-01-27 09:03:22 +01:00
Florent Kermarrec e8be391504 setup.py: Deprecate lxterm/lxserver/lxsim short names. 
These were no longer really used and was confusing.
 2022-01-26 15:14:54 +01:00
Florent Kermarrec 6b4d5cd3e1 README: Add --config to install command. 2022-01-26 14:51:54 +01:00
Florent Kermarrec af26d939d0 litex_setup: Declare python3 in top and use it. 2022-01-26 14:49:02 +01:00
enjoy-digital f82f769794
Merge pull request #1185 from benstobbs/master 
litex_setup.py on Windows: Change install "python3" to current interpreter
 2022-01-26 14:45:00 +01:00
Florent Kermarrec 4ab45d72a8 litex_setup: Add --status argument to display Git status of repositories. 2022-01-26 14:44:04 +01:00
Florent Kermarrec d2d8d902e1 litex_setup/print_status: Add underline parameter and use it. 2022-01-26 14:20:41 +01:00
Florent Kermarrec 419d605e38 build/toolchains: Specify passed toolchain when unknown. 2022-01-26 11:56:22 +01:00
Ben Stobbs e0149eb814 change repo install python interpreter to current interpreter 2022-01-25 22:46:33 +00:00
enjoy-digital 3020344fd8
Merge pull request #1184 from trabucayre/yosys_nextpnr_zynq 
litex/build/xilinx/yosys_nextpnr: adding zynq7 and xc7z010 & xc7z020 support
 2022-01-25 22:27:01 +01:00
enjoy-digital 7acdac2e51
Merge pull request #1183 from trabucayre/fix_yosys_synth 
litex/soc/cores/clock/xilinx_common: fix yosys synth: replace FD by FDCE
 2022-01-25 22:26:18 +01:00
Gwenhael Goavec-Merou f00fe1b1d8 litex/build/xilinx/yosys_nextpnr: adding zynq7 and xc7z010 & xc7z020 support 2022-01-25 21:58:03 +01:00
Gwenhael Goavec-Merou f8acc5f506 litex/soc/cores/clock/xilinx_common: fix yosys synth: replace FD by FDCE 2022-01-25 21:44:02 +01:00
Florent Kermarrec 77c6cdd78e cores/clocks/lattice_ecp5: Rename ECP5Delay to ECP5DynamicDelay and adapt style for consistency. 2022-01-25 11:09:15 +01:00
Florent Kermarrec ea6bb3dd80 test/test_clock: Add minimal ECP5Delay test (syntax), rename tests with underscore. 2022-01-25 10:49:33 +01:00
enjoy-digital 6ff8b6e4ed
Merge pull request #1173 from sergachev/ecp5_delay 
clock/lattice_ecp5: add ECP5 dynamic delay DELAYF primitive support
 2022-01-25 10:44:53 +01:00
enjoy-digital d059111c92
Merge pull request #1180 from suarezvictor/master 
Add yosys+nextpnr toolchain support
 2022-01-24 19:02:02 +01:00
Victor Suarez Rovere 6d7f8888ac Add yosys+nextpnr toolchain support 2022-01-24 13:35:12 -03:00
enjoy-digital 6b3eda16f2
Merge pull request #1179 from Technosystem-Labs/vexriscv_hw_breakpoints 
Added Vexriscv hardware breakpoint variants for Mini and Lite.
 2022-01-24 08:16:39 +01:00
Mikolaj Sowinski 9e0d8b3f41 Added Vexriscv hardware breakpoint variants for Mini and Lite. 2022-01-24 00:00:26 +01:00
enjoy-digital 8d3f12ebbd
Merge pull request #1178 from sergachev/gowin_emcu 
Enable LiteX BIOS on Gowin EMCU ARM core
 2022-01-23 21:01:06 +01:00
enjoy-digital 57fef500a7
Merge pull request #1177 from yetifrisstlama/i2c 
bitbang.py: initialize SCL / SDA lines to high on reset
 2022-01-23 21:00:20 +01:00
Ilia Sergachev f36619987b software/bios: update comment 2022-01-23 16:57:33 +01:00
Ilia Sergachev 85f892227a cores/cpu/gowin: re-enable write access to csr bus 2022-01-23 16:34:47 +01:00
Michael Betz e4ceaa7cc2
bitbang.py: initialize SCL / SDA lines to high on reset 
* otherwise might block the I2C bus on reset
 2022-01-23 16:11:34 +01:00
Ilia Sergachev 0f44723957 cores/cpu/gowin: fix isr table optimization and uart init 2022-01-23 15:37:00 +01:00
Ilia Sergachev d4c12a5231 cores/cpu/gowin_emcu: add software support 2022-01-23 11:20:44 +01:00
Ilia Sergachev 3f2a7b9bfd software/bios: set attribute used on main to fix optimization in some configurations 2022-01-23 11:04:22 +01:00