ce96668ebd
integration/soc: Fix typo.
2021-11-14 09:43:00 +01:00
8d7196d567
cpu/eos_s3: Cleanup clocking.
2021-11-14 09:18:53 +01:00
c30df687b4
cpu/eos_s3: First cleanup pass.
2021-11-14 09:10:26 +01:00
bce2297418
cpu/eos_s3: Put wishbone bus in periph_buses and avoid specific integration.
2021-11-14 09:02:53 +01:00
e612f0d1ec
Merge pull request #1102 from trabucayre/eos_s3_fix_wb_adr
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Eos s3 fix wb adr
2021-11-14 08:50:32 +01:00
b703980c86
soc/cores/cpu/eos_s3: fix o_WBs_ADR align
2021-11-13 18:33:29 +01:00
291402608e
efinix/ifacewriter: Renamer br0_pll to dram_pll.
2021-11-12 19:44:20 +01:00
0a90a0eee9
cpu/vexriscv_smp: Use specific Ram_1w_1rs implementation on Efinix FPGAs.
2021-11-12 18:00:47 +01:00
1ce2073694
soc/cores/cpu/eos_s3: add interrupt support
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Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
2021-11-12 13:20:16 +01:00
ea04273281
soc/cores/cpu/eos_s3: add interrupt support
2021-11-12 11:34:03 +01:00
f679992f8d
efinix/ifacewriter/add_dram_xml: Switch ctrl_type to ena_user_rst.
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Also add notes for future improvements.
2021-11-11 12:26:26 +01:00
f89e883ab0
soc/cores/clock/efinix_trion: Add clock constraints to PLL's clkouts.
2021-11-11 11:44:35 +01:00
55ac0d4bd8
build/efinix/efinity: Generate bitstreams to gateware directory.
2021-11-11 11:18:32 +01:00
371319023e
build/efinix: Build is better with colors!
2021-11-11 11:10:58 +01:00
1932506373
build/efinix/efinity: Simplify/Cleanup pass and only keep mandatory information in project's xml.
2021-11-11 11:10:48 +01:00
a5356f78c3
build/efinix/efinity: Switch to direct call of efx_map/pnr/pgm and add family parameter.
2021-11-11 11:07:23 +01:00
a89772f087
Merge pull request #1098 from Technosystem-Labs/liblitedram_fix
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liblitedram: Write latency calibration failure fix
2021-11-11 09:00:18 +01:00
ee605540bf
build/efinix/efinity: Prepare build switch to direct calls of efx_map/efx_pnr/efx_pgm.
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Will give us more flexibily and to display build infos.
2021-11-10 19:47:00 +01:00
873a0d4e17
efinix/ifacewriter/generate_pll_dram: Change name to br0_pll for now (to be as close as possible from the example design).
2021-11-10 19:42:01 +01:00
fd6162c87f
Make use of _sdram_write_leveling_bitslips in write latency calibration only for write leveling capable targets
2021-11-10 14:01:15 +01:00
feca1c472d
build/efinix/ifacewriter: Go a bit further in DRAM integration.
2021-11-10 12:05:47 +01:00
a742731d26
cpu: Add initial EOS-S3 Integration.
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Initial support allowing Software control of the Leds in the eFPGA.
2021-11-09 18:55:53 +01:00
f89b99eccc
build/efinix/ifacewriter: Add initial add_ddr_xml with LPDDR3/1 256-bit AXI Port.
2021-11-09 16:12:30 +01:00
d806b880a0
build/efinix: Add add_iface_ios.
2021-11-09 16:11:21 +01:00
aec8276cdb
build/efinix/ifacewriter: Cosmetic cleanup (Replace " with ' when possible) and move add_ddr_lvds to the end.
2021-11-09 14:29:00 +01:00
02c0ed2de7
bios/boot: Fix memcpy exceeding length (Thanks @acathla).
2021-11-09 14:04:40 +01:00
7b259888bb
bios/boot: Cosmetic cleanup.
2021-11-09 14:03:30 +01:00
0c028d1614
clock/efinix_trion: Add n parameter, rename pll_name to name.
2021-11-09 11:19:27 +01:00
7aac228690
cores/clock/efinix_trion: Revert use of name as clk_out_name when specified.
2021-11-08 19:39:05 +01:00
95a68609cd
clock/efinix_trion: Minor cleanup, revert support to None cd in create_clkout.
2021-11-08 18:19:12 +01:00
af5167c7f0
soc/interconnect/axi: Fix beat_offset dimension (was limiting bursts to 2KB instead of 4KB).
2021-11-05 18:39:22 +01:00
f0e3b3f3ea
cores/cpu/femtorv: Fix and used already patched version.
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Integration will still have to be finished: https://github.com/enjoy-digital/litex/issues/1096 .
2021-11-05 17:44:06 +01:00
1aee3ba72e
cores/cpu/ibex: Remove patch (no longer required).
2021-11-05 17:19:17 +01:00
2740dd34e7
sim/verilator: Revert regular_comb change and just pass it to get_verilog as before.
2021-11-05 16:27:38 +01:00
67431f4109
cores/led: Add initial WS2812/NeoPixel core (MMAPed).
2021-11-04 08:41:00 +01:00
c13be522ce
Merge pull request #1094 from mkj/matt/sim-regular-comb
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litex_sim: Allow regular_comb=False argument
2021-11-02 15:04:42 +01:00
1716e37809
litex_sim: Allow regular_comb=False argument
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This was removed in
3b78fd928d
2021-11-02 18:16:28 +08:00
9ecb1e61a9
fhdl/verilog: Fix sig.direction regression.
2021-10-31 23:40:11 +01:00
3ba5d6f187
Merge pull request #1093 from cr1901/ccache
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Add option in Makefile for (s)ccache support.
2021-10-30 22:49:32 +02:00
1eaece22d3
Merge pull request #1092 from enjoy-digital/verilog-dev
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fhdl/verilog: Improve code presentation.
2021-10-30 22:48:21 +02:00
e9dd07006e
Merge pull request #1091 from enjoy-digital/memory-dev
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fhdl/memory: Improve generation code and avoid specific generation for Efinix FPGAs.
2021-10-30 22:47:59 +02:00
28c8436e01
fhdl/memory/write: Avoid slicing data when memory.width == port.we_granularity.
2021-10-30 22:42:55 +02:00
86ef4e95a5
Add option in Makefile for (s)ccache support.
2021-10-29 21:04:05 -04:00
942e50b992
fhdl/verilog: Improve code presentation.
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- Add a LiteX Header/Trailer.
- Add _print_signal function.
- Add more infos to the Header.
- Add separators between blocks of code.
- Align Wire/Reg definition.
2021-10-28 20:14:35 +02:00
08a9392c54
fhdl/memory: Simplify Read Logic.
2021-10-28 14:34:52 +02:00
576bb67332
fhdl/memory: Simplify Write Logic (Avoid specific cases on write granuarity).
2021-10-28 14:19:35 +02:00
d86cd94c71
efinix/memory: Avoid specific memory_efinix generator by applying FullMemoryWE on the design.
2021-10-28 12:11:40 +02:00
3d4e45145d
fhdl/memory: Simplify logic generation and improve intermediate address/data register naming.
2021-10-28 11:25:53 +02:00
95e5f20bd8
fhdl/memory: Simplify Write Logic generation when with granularity.
2021-10-28 11:11:09 +02:00
b6c4f6ae24
fhdl/memory: Add initial Memory description.
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Gives an overview of the generated Verilog Memory, will be useful for debug/improve inference.
2021-10-28 10:51:58 +02:00
Florent Kermarrec
Gwenhael Goavec-Merou
Mikołaj Sowiński
Matt Johnston
William D. Jones