87d7f6e72e
Merge pull request #598 from sergachev/master
...
interconnect/csr_bus: fix paged access warning
2020-07-20 19:24:21 +02:00
8656ea9b67
interconnect/csr_bus: fix paged access warning
2020-07-20 18:23:09 +02:00
4a18b828bc
software/liblitesdcard/spisdcard: remove optimization on receive_block (not working on all configs) and increase max clk_freq to 20MHz.
2020-07-20 13:48:49 +02:00
100aa5a4ca
soc/cores/spi/SPIMaster: rewrite/simplify.
...
- Make sure MOSI is latched on start, MISO is stable during Xfer (last value).
- Allow clk_divider down to 2.
- improve test errors reporting with hex() on AssertEqual.
2020-07-20 10:44:18 +02:00
63c19ff45f
liblitesdcard/spisdcard: update comments.
2020-07-17 15:39:39 +02:00
1f34f6ef00
soc/cores/spi: make sure done and miso are synchronous.
2020-07-17 15:38:52 +02:00
754f140a9d
spisdcard: revert to 8-bit SPI, optimize spisdcardreceive_block and reduce clk to 12.5MHz for now.
2020-07-17 11:58:26 +02:00
8143f1a08b
soc/cores/spi: make sure miso is stable during xfer.
2020-07-17 11:56:27 +02:00
ac35e158c1
bios/boot: add bootargs support on netboot/sdcardboot to optionally specify r1/r2/r3/addr.
...
For example:
{
"Image": "0x40000000",
"bootargs": {
"r1": "0x12345678",
}
}
will copy Image to 0x40000000 and set r1 to 0x12345678.
By default, r1,r2,r3 are set to 0 and addr is the address if the last loaded image, so:
{
"Image": "0x40000000",
"rootfs.cpio": "0x40800000",
"rv32.dtb": "0x41000000",
"emulator.bin": "0x41100000",
}
is equivalent to:
{
"Image": "0x40000000",
"rootfs.cpio": "0x40800000",
"rv32.dtb": "0x41000000",
"emulator.bin": "0x41100000",
"bootargs": {
"r1": "0x00000000",
"r2": "0x00000000",
"r3": "0x00000000",
"addr": "0x00000000",
}
}
2020-07-16 18:12:11 +02:00
ee4b1d81a7
Merge pull request #594 from antmicro/jboc/axi-lite
...
Add AXILiteDownConverter
2020-07-16 17:56:33 +02:00
229da572ff
soc/interconnect/axi: propagate response errors in AXILiteDownConverter
2020-07-16 17:16:35 +02:00
93bcc94b53
soc/interconnect/axi: implement AXILite down-converter
2020-07-16 17:02:49 +02:00
21c48eed76
Merge pull request #593 from antmicro/jboc/axi-lite
...
Add AXILite components: AXILiteSRAM and AXILite2CSR
2020-07-16 11:56:57 +02:00
0be607dad9
soc/integration: revert `bus` argument for add_ram/add_rom
2020-07-16 10:26:12 +02:00
2700ec3ce5
soc/integration: use AXILiteConverter (dummy implementation) in add_adapter()
2020-07-15 15:59:16 +02:00
f3072d4984
soc/interconnect/axi: add connect methods for convenience
2020-07-15 15:48:40 +02:00
78a631f392
test/axi: add AXILite2CSR and AXILiteSRAM tests
2020-07-15 12:40:39 +02:00
e12bebb8e1
Merge pull request #592 from antmicro/fix-symbiflow-makefile
...
symbiflow: changed toolchain command names in Makefile
2020-07-15 12:08:21 +02:00
a5be2cd257
soc/interconnect/axi: improve SRAM/CSR access speed
2020-07-15 11:44:14 +02:00
3f7568de09
symbiflow: changed toolchain command names in Makefile
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-07-15 11:31:06 +02:00
d8a242d86f
soc/interconnect: add AXILite SRAM
2020-07-15 10:58:34 +02:00
b692b2a3f1
soc/interconnect: add AXILite2CSR bridge
2020-07-15 10:36:34 +02:00
35149c4e80
soc/integration: update add_adapter to convert between AXILite/Wishbone
2020-07-14 16:31:46 +02:00
6671eb6218
build/lattice/trellis: set default spimode to None (--spimode not passed to ecppack) as default instead of fast-read.
...
Using fast-read as default prevent loading the .bit via JTAG (see #589 ).
2020-07-13 11:55:03 +02:00
ae3c78f6d1
build/lattice/trellis: fix spimode typo.
2020-07-11 21:30:19 +02:00
7c381dadc2
Merge pull request #588 from oskirby/trellis-spimode
...
trellis: Add option to select SPI mode.
2020-07-11 21:26:55 +02:00
0aec5b0f8c
trellis: Add option to select SPI mode.
...
This allows a significant speedup when booting large bitstreams on ECP5
boards that support dual or quad SPI operation.
2020-07-11 11:48:10 -07:00
e76464167b
Merge pull request #587 from antmicro/mor1x_ror_instruction
...
mor1kx: Do not generate the ror instruction
2020-07-10 11:21:13 +02:00
468db3cf08
integration/soc/sdcard: add mode parameter to enable read only, write only or read+write modes.
2020-07-10 11:18:22 +02:00
b8d900862c
mor1kx: Do not generate the ror instruction
...
The mor1kx core does not support `l.ror` instruction
by default, but gcc/clang flags allowed the
compiler to generate it.
2020-07-10 11:07:12 +02:00
b7e4507686
core/cpu/CPUNone: set endianness to little.
2020-07-10 10:42:00 +02:00
0eb1f88bb4
Merge pull request #585 from FFY00/more-gcc
...
cpu: add a few missing GCC toolchains
2020-07-09 09:34:22 -07:00
235e8cf62b
cpu: add a few missing GCC toolchains
...
This names are used by Arch Linux for eg.
Signed-off-by: Filipe Laíns <lains@archlinux.org>
2020-07-09 15:58:33 +01:00
5ebdfd9307
liblitesdcard/sdcard: clamp divider value.
2020-07-09 13:09:36 +02:00
23085cffea
Merge pull request #584 from ozbenh/memtest
...
Memtest/memspeed improvements
2020-07-09 12:54:42 +02:00
5c332e4b58
cores/dma: add stream.last support on WishboneDMAReader.
2020-07-09 12:18:09 +02:00
83d24d087d
memspeed: Write a fixed value
...
Otherwise we have at least an extra addition in the loop
which squews the result compared to the read loop.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-07-08 17:13:37 +10:00
146ead4c4c
buid/io/InferedSDRIO/InferedSDRTristate: avoid unnecessary clk_domain/limitation.
...
Just create a local clk_domain from clk signal.
2020-07-08 08:33:52 +02:00
b54b3b3362
interconnect/avalon: minor cleanup, remove max on SyncFIFO depth.
2020-07-08 07:53:42 +02:00
c0b948d4f9
memtest: Fix memspeed access size
...
The move to libbase reverted the type of the pointer
from long to int.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-07-08 13:21:45 +10:00
798b3d7ba4
memtest: Fix integer size/type printf errors
...
In a couple of places, memtest uses %x to print a pointer which
is illegal (and could be problematic on 64-bit). Use %p instead.
Additionally, use %ld when printing longs
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-07-08 13:17:48 +10:00
8af4e05c7f
software/litesdcard: use new clocking and use slow clock during initialization.
2020-07-07 19:59:50 +02:00
52f36b1257
integration/soc/sdcard: cleanup emulator integration, fix sim.
2020-07-07 15:05:07 +02:00
7602977c16
integration/soc: move pads.rst control to PHY.
2020-07-07 14:58:06 +02:00
51f2e6ce64
build/io/InferedSDRTristate: pass clock domain to SDROutput/SDRInput.
2020-07-07 12:11:47 +02:00
23dfefb9be
software/liblitesdcard: improve sdcard_init and handle errors.
2020-07-07 11:03:26 +02:00
8d76509032
litesdcard: use new Block2Mem/Mem2Block DMAs.
2020-07-07 09:24:08 +02:00
eeea30eada
litex/gen: remove io that has been replaced with litex/build/io (and should have been removed).
2020-07-07 08:14:42 +02:00
0a3095ead2
Merge pull request #583 from gsomlo/gls-sdcard-timeout
...
liblitesdcard/sdcard: adjust card-ready timeout
2020-07-07 08:06:55 +02:00
6fdb36b84a
liblitesdcard/sdcard: adjust card-ready timeout
...
Testing on nexys4ddr and rocket, approximately 12 iterations of the
timeout loop (using `busy_wait(1)`) are needed to receive a "ready"
response from the SDcard, assuming a "warm" reset where the card has
already been previously initialized.
If the SDcard is ejected and re-inserted, or if the board is "cold-reset"
(e.g., reprogrammed via openocd vs. a simple push of the reset button),
it takes approximately 450 iterations before the SDCard responds with a
"ready" message.
In either case, a timeout of 10 is insufficient. This patch increases
the busy-wait to 10, and the timeout loop counter to 128, which should
cover most cases.
Additionally, make a few minor cosmetic improvements.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-07-06 17:38:07 -04:00
enjoy-digital
Ilia Sergachev
Jędrzej Boczar
Alessandro Comodi
Owen Kirby
Mateusz Holenko
Tim Ansell
Filipe Laíns
Benjamin Herrenschmidt
Gabriel Somlo