9548259a5c
gen/fhdl/namer: Simplify build_namespace and add comments.
2023-11-06 12:31:48 +01:00
a65d471ed2
gen/fhdl/namer: Simplify _invert_pnd_build_signal_groups/_build_pnd and add comments.
2023-11-06 11:58:29 +01:00
36e47052b2
gen/fhdl/namer: Simplify _invert_pnd/_list_conflicting_signals/_set_use_number/_build_pnd_for_group and add comments.
2023-11-06 11:49:48 +01:00
d28b7a1172
gen/fhdl/namer: Simplify _set_use_name/_build_pnd_from_tree and add comments.
2023-11-06 11:32:52 +01:00
6214aa69af
gen/fhdl/namer: Simplify _build_tree and add comments.
2023-11-06 10:52:44 +01:00
1e805a8789
fhdl/namer: Remove debug and add docstring comments.
2023-11-06 09:38:17 +01:00
6aa22271f9
Merge pull request #1825 from enjoy-digital/verilog_improvements
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Verilog improvements
2023-11-06 09:11:40 +01:00
2beeca4c95
Merge pull request #1827 from enjoy-digital/video_framebuffer_skip_first_frame
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cores/video/VideoFramebuffer: Skip first frame on enable to ensure pr…
2023-11-06 09:11:26 +01:00
b0c0669ed3
cores/video/VideoFramebuffer: Skip first frame on enable to ensure proper VTG/DMA synchronization.
2023-11-05 08:18:43 +01:00
f4e68d78ca
cores/video: Fix missing h/vsync connection in SYNC state.
2023-11-04 20:55:56 +01:00
6f431fa2b1
gen/fhdl: Cleanup/Simplify hierarchy generation.
2023-11-03 14:57:48 +01:00
a1704a045e
gen/fhdl/instance: Ident Parameters/IOs on max length of names.
2023-11-03 12:31:14 +01:00
4627e8958f
gen/fhdl/instance: Generate Parameters/Inputs/Outputs/InOuts separators and generate IOs in Input/Output/InOut order.
2023-11-03 12:11:53 +01:00
18c0541e6a
gen/fhdl/instance: Add instance description.
2023-11-03 11:53:32 +01:00
079a0a7b75
gen/fhdl/instance: First cleanup pass.
2023-11-03 11:47:07 +01:00
dee64b346f
gen/fhdl: Integrate Migen's Instance verilog generation to be able to customize it to our needs.
2023-11-03 11:40:16 +01:00
fe19ee464e
gen/fhdl/memory: Rename memory_emit_verilog to _memory_generate_verilog.
2023-11-03 11:29:48 +01:00
e6d950bcb0
gen/fhdl/verilog: Add module hierarchy generation after module definition.
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Will give a better overview of the generated verilog and will also ease comparing changes/track regressions.
2023-11-03 11:08:40 +01:00
4a1486b1db
gen/fhdl/hierarchy: Add with_colors parameters to allow enabling/disabling colors.
2023-11-03 11:06:41 +01:00
4497569118
gen/context: Rename soc to top.
2023-11-03 11:05:57 +01:00
27c55999c6
gen/common/colorer: Add enable parameter to allow enabling/disabling coloring.
2023-11-03 11:05:09 +01:00
1f200c83f3
build: Minor cleanups on get_verilog calls.
2023-11-03 11:04:31 +01:00
b60bd92533
gen/fhdl/verilog: Rename _print_xy to _generate_xy and cleanup imports.
2023-11-03 10:14:38 +01:00
71ae8fe828
Merge pull request #1824 from trabucayre/add_64_bus_support_v2
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soc/interconnect/wishbone: InterconnectShared,Crossbar: using master adr_width for Interface constructor
2023-10-31 21:17:31 +01:00
755808e287
soc/interconnect/wishbone: InterconnectShared,Crossbar: using master adr_width for Interface constructor
2023-10-31 11:59:49 +01:00
9b8a5b6385
CHANGES: Update.
2023-10-30 19:40:42 +01:00
8c73afea91
Merge pull request #1823 from trabucayre/cpuNone_config
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litex/soc/cores/cpu/__init__, litex/soc/integration/soc: modifying CPUNone to adapt data_width and io_regions according to bus data_width/address_width
2023-10-30 18:42:54 +01:00
16133359d6
soc/integration/soc: fix typo at UARTBone call (addr_width -> address_width)
2023-10-30 18:13:46 +01:00
eedebd8adb
litex/soc/cores/cpu/__init__, litex/soc/integration/soc: modifying CPUNone to adapt data_width and io_regions according to bus data_width/address_width
2023-10-30 17:17:16 +01:00
4b9601bdab
Merge pull request #1822 from trabucayre/rework_tools
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tools: litex_server, litex_client and remote: don't hardcode bus address
2023-10-30 17:13:46 +01:00
a2c39a7bbf
tools: litex_server, litex_client and remote: don't hardcode bus address
2023-10-30 16:20:31 +01:00
5efdbd9c20
Merge pull request #1821 from trabucayre/uartbone_add_width
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UARTBone addr width
2023-10-30 15:03:37 +01:00
321254cc38
soc/integration/soc: pass bus.address_width to UARTBone constructor
2023-10-30 11:14:30 +01:00
f06ef5205a
soc/cores/uart: adding address_width (default 32bits) to UARTBone constructor
2023-10-30 11:13:40 +01:00
9374196974
soc/cores/uart: allows 64bits in Stream2Wishbone
2023-10-30 11:03:16 +01:00
b5a9106f56
cores/video: Simplify VTG/DMA synchronization and re-synchronize on each end of frame.
2023-10-27 18:09:03 +02:00
5842ad7d14
Merge pull request #1818 from Dolu1990/nax-smp
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core/naxriscv update to main branch
2023-10-27 16:32:28 +02:00
5e482d641c
core/naxriscv switch to main branch, and implement a reset controller internaly
2023-10-27 16:06:07 +02:00
d021564fca
interconnect/wishbone: Revert SRAM to Module, needs to be investigated.
2023-10-27 15:24:57 +02:00
ff271b0b5f
Merge pull request #1816 from motec-research/test_csr_status_issue
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test_csr: test cases to demonstrate a CSRStatus() issue
2023-10-27 12:52:25 +02:00
c44b906d9f
interconnect/stream: Revert Convert to Module, needs to be investigated.
2023-10-27 12:33:37 +02:00
856d7452b3
gen/fhdl/module: Ensure Module/Special/ClockDomains are initialized before adding them as submodules/specials/clock_domains.
2023-10-27 12:26:54 +02:00
fa629b782f
CHANGES: Update.
2023-10-27 11:40:31 +02:00
e55cf0f6d9
Merge pull request #1804 from zeldin/ecp5_pll_phase
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cores/clocks/lattice_ecp5: Fix phase calculation to match Diamond output
2023-10-27 11:37:50 +02:00
63159aa187
soc/cores: Minor cosmetic changes.
2023-10-27 11:29:38 +02:00
48f27707d1
soc/cores: Make sure all Modules are switched to LiteXModule.
2023-10-27 11:16:55 +02:00
a2820cba96
interconnect/packet: Switch to LiteXModule.
2023-10-27 11:07:31 +02:00
fa521f5c89
interconnect/wishbone: Switch to LiteXModule.
2023-10-27 11:05:37 +02:00
9ccac7f7e0
interconnect/stream: Switch to LiteXModule.
2023-10-27 11:03:33 +02:00
002aad7a43
soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.
2023-10-27 10:55:13 +02:00
Florent Kermarrec
Gwenhael Goavec-Merou
Dolu1990