Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity
955 commits 42 branches 14 tags 31 MiB
Commit graph

228 commits

Author SHA1 Message Date
Robert Jordens
44c6e524ba migen.fhdl.structure: add Signal.like(other) 
This is a convenience method. Signal(flen(other)) is used frequently but that
drops the signedness. Signal((other.nbits, other.signed)) would be correct but
is long.
 2014-07-24 23:52:59 -06:00
Sebastien Bourdeauducq
29ed3918cc fhdl: forbid zero-length signals 2014-04-18 15:01:50 +02:00
Sebastien Bourdeauducq
90f0dfad63 Add 'passive' simulation functions that are not taken into account while determining when to stop the simulator 2014-01-27 23:58:46 +01:00
Sebastien Bourdeauducq
63c1d7e4b7 New simulation API 2014-01-26 22:19:43 +01:00
Robert Jordens
be1c8551d2 migen/fhdl/tools: speed up group_by_targets (halves the mixxeo runtime) 2013-12-17 18:40:49 +01:00
Sebastien Bourdeauducq
a20688f777 fhdl/simplify/FullMemoryWE: fix WE slice for multi-port mems 2013-12-13 00:02:50 +01:00
Sebastien Bourdeauducq
adda930c68 fhdl/simplify: add FullMemoryWE decorator that splits memories to remove partial WEs 2013-12-12 17:37:31 +01:00
Sebastien Bourdeauducq
c13fe1bc63 specials/Memory: allow for more flexibility in memory port signals 2013-12-12 17:36:17 +01:00
Sebastien Bourdeauducq
135a4fea25 fhdl/verilog: fix representation of negative integers 
Give the explicit two's complement representation for the given bit width.

This results in less readable code compared to using unary minus,
but fixes a bug when trying to represent the most negative integer.
 2013-12-11 22:26:10 +01:00
Robert Jordens
487df5b174 migen/fhdl/bitcontainer: fix signed arrays (map is an iterator) 2013-12-10 23:32:12 +01:00
Robert Jordens
8d3d61ba98 fhdl.size: rename to bitcontainer 2013-12-03 22:51:52 +01:00
Robert Jordens
86ba9c8bbc migen.fhdl.size: verify fslice for negative values 2013-12-03 21:39:37 +01:00
Robert Jordens
c71eb5778f migen.fhdl.structure: have Cat() flat_iteration-ize its arguments 2013-12-03 21:36:33 +01:00
Robert Jordens
1bf133755e migen.fhdl.tools: move flat_iteration to migen.util.misc as tools imports other things 2013-12-03 21:36:33 +01:00
Robert Jordens
fe67210d77 migen.fhdl.size: add fiter(), fslice(), and freversed() 
do not overload __len__, __iter__, __reversed__ as not all valid
expressions (ints and bools) have them. furthermore len([]) is and
should be different from flen([]) (the later raises an error). keep
__getitem__ as an exception that proves the rule ;)
 2013-12-03 21:36:33 +01:00
Sebastien Bourdeauducq
be9fea182d fhdl/structure: clarify usage restrictions of LHS Cat 2013-11-29 22:35:53 +01:00
Robert Jördens
73db4944f1 fhdl.structure: document the API 2013-11-29 22:31:55 +01:00
Sebastien Bourdeauducq
fa741f54fd specials/Instance: add PreformattedParam 2013-11-25 12:09:51 +01:00
Sebastien Bourdeauducq
f658802ff8 replace use of __dict__ with dir()/xdir() 2013-11-02 16:03:47 +01:00
Nina Engelhardt
6f9f08f6eb add ternary operator sel ? a : b 2013-08-12 13:15:56 +02:00
Nina Engelhardt
e12187aa80 add += operator to fragment 2013-08-12 13:15:05 +02:00
Sebastien Bourdeauducq
fdf022a04b fhdl: improve naming of related signals 2013-08-08 19:22:17 +02:00
Sebastien Bourdeauducq
2c580fff03 fhdl/namer: detect leaf nodes better 2013-08-08 12:22:58 +02:00
Sebastien Bourdeauducq
eb1417c5ed fhdl: move insert_resets to tools 2013-08-08 11:32:58 +02:00
Sebastien Bourdeauducq
305c6985bc fhdl: support for naming related signals 2013-08-08 11:32:37 +02:00
Sebastien Bourdeauducq
146a1b5d51 namer: add HUID suffix step 2013-08-08 00:15:18 +02:00
Sebastien Bourdeauducq
fd34b75fb4 namer: split by numbers 2013-08-07 23:22:40 +02:00
Sebastien Bourdeauducq
7a243171bd fhdl/namer: new namer with explicit tree 2013-08-07 17:13:52 +02:00
Nina Engelhardt
efa7dc9cf4 fhdl/edif: adjust for use with mibuild 2013-08-03 10:54:06 +02:00
Nina Engelhardt
7372c7a97c fhdl/edif: add support for inout signals 2013-08-03 10:51:24 +02:00
Nina Engelhardt
17002fb05e fhdl: add EDIF back-end 2013-07-31 22:47:43 +02:00
Nina Engelhardt
61b8958953 fix synthesis translate on/off switch 2013-07-26 15:55:16 +02:00
Sebastien Bourdeauducq
9c7ad6b05b fhdl: RenameClockDomains decorator 2013-07-26 15:42:14 +02:00
Sebastien Bourdeauducq
cec8fc4ca4 fhdl/specials/Instance: fix item sorting 2013-07-26 14:00:29 +02:00
Sebastien Bourdeauducq
b96eb339af fhdl: compact Instance syntax 2013-07-25 20:34:19 +02:00
Sebastien Bourdeauducq
b7ed19c6c5 fhdl: do not export Fragment 2013-07-25 18:52:54 +02:00
Sebastien Bourdeauducq
b367932498 fhdl: introduce module decorators 2013-07-25 17:56:31 +02:00
Sebastien Bourdeauducq
411e6ec114 fhdl/tools: do not export resort_statements 2013-07-17 16:50:09 +02:00
Sebastien Bourdeauducq
d5d2e64dc3 Revert "fhdl/tools/group_by_target: remove resort_statements" 
This reverts commit 939f01cee2.
 2013-07-17 16:49:26 +02:00
Sebastien Bourdeauducq
939f01cee2 fhdl/tools/group_by_target: remove resort_statements 2013-07-17 10:38:39 +02:00
David Carne
16ebe41028 fhdl/tools: BUGFIX: fix group_by_target grouping 
group_by_target does not properly combine target groups if statements
are presented in the order:

 ({A}, statement1)
 ({B}, statement2)
 ({A, B}, statement3)

which returns groups:

 ({A, B}, [statement1, statement3])
 ({B}, [statement2])

This patch fixes group_by_target such that the resulting group is:

 ({A, B}, [statement1, statement2, statement3])
 2013-07-17 10:14:39 +02:00
David Carne
faa8b7c49a fhdl/tools: clock domain merging for clock renaming 2013-07-16 18:17:44 +02:00
Sebastien Bourdeauducq
04efee7847 fhdl: mark variable as deprecated 2013-06-30 20:14:20 +02:00
Sebastien Bourdeauducq
71b89e4c46 fhdl/verilog: lower complex slices before reset insertion 2013-06-30 14:32:47 +02:00
Sebastien Bourdeauducq
ded5e569eb fhdl/tools: separate complex slice lowerer from basic lowerer 2013-06-30 14:32:19 +02:00
Robert Jördens
a255296171 support re-slicing and non-unit step size 
* support slicing of Slice/Cat/Replicate through lowering
* support non-unit step size slices through unpacking and Cat()
 2013-06-30 14:03:34 +02:00
Sebastien Bourdeauducq
080afdc3f9 fhdl/verilog: fix signedness rules for comparison 2013-06-26 22:45:47 +02:00
Sebastien Bourdeauducq
b56cb3cefc fhdl/verilog: improve error reporting 2013-06-24 19:44:25 +02:00
Sebastien Bourdeauducq
f0b0942055 bitreverse: fhdl/tools -> genlib/misc 2013-05-30 18:44:37 +02:00
Sebastien Bourdeauducq
bac62a32a9 Make memory ports part of specials 
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
 2013-05-28 16:11:34 +02:00