Florent Kermarrec
|
bc81d9d639
|
liteeth/phy/__init__.py: add more comments
|
2015-04-12 18:56:46 +02:00 |
|
Florent Kermarrec
|
515398634f
|
liteeth/phy/gmii_mii: add clock counter and use it in bios to select mode
|
2015-04-12 18:42:52 +02:00 |
|
Florent Kermarrec
|
857bee8a00
|
liteeth/phy: add GMII/MII phy
for now swicth is manual, we will need a clk counter to allow software or logic to automatically switch between GMII and MII
|
2015-04-12 17:25:55 +02:00 |
|
Florent Kermarrec
|
cfac3d9f5c
|
liteeth/phy/mii: simplify LiteEthPHYMIIRX using Converter
|
2015-04-12 16:03:21 +02:00 |
|
Florent Kermarrec
|
ddae41f2e4
|
liteeth/phy/mii: simplify LiteEthPHYMIITX using Converter
|
2015-04-12 15:34:56 +02:00 |
|
Florent Kermarrec
|
8c722db54e
|
liteeth/phy/mii: assign tx_er only if exists (as it's done on GMII)
|
2015-04-12 14:43:35 +02:00 |
|
Florent Kermarrec
|
4329e3e1b9
|
liteeth/phy/mii: allow use of MII phy on GMII/MII chips that do not have phy clock provided by the FPGA (tested on KC705)
|
2015-04-12 14:28:17 +02:00 |
Sebastien Bourdeauducq
|
603a4ef51e
|
liteeth: adapt to new ModuleTransformer
|
2015-04-10 11:42:25 +08:00 |
|
Florent Kermarrec
|
03aa972bb6
|
lite*: finish ModuleTransformer adaptations (need to be tested on board)
|
2015-04-08 23:27:22 +02:00 |
Robert Jordens
|
66f8dcbfaf
|
lite*: adapt to new ModuleTransformer semantics
NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
|
2015-04-04 19:17:24 +08:00 |
|
Sebastien Bourdeauducq
|
696819cc7f
|
move gpio from cpu.peripherals to com
|
2015-04-02 17:17:33 +08:00 |
|
Florent Kermarrec
|
dcdf5df4de
|
adapt LiteEth to new SoC
|
2015-04-01 22:50:29 +02:00 |
|
Florent Kermarrec
|
20207c9c32
|
liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6)
|
2015-03-22 11:11:37 +01:00 |
|
Florent Kermarrec
|
c77562f44b
|
liteusb: make oe_n optional on ft2232h phy
|
2015-03-22 10:56:56 +01:00 |
|
Florent Kermarrec
|
ed5746a1fe
|
liteusb: fix imports
|
2015-03-22 10:56:29 +01:00 |
|
Florent Kermarrec
|
9107710f03
|
litexxx cores: use default baudrate of 115200 for all tests
|
2015-03-20 12:22:53 +01:00 |
|
Florent Kermarrec
|
84b631c929
|
liteeth/mac/core: add with_padding option (enabled by default) and change with_hw_preamble_crc option to with_preamble_crc
|
2015-03-19 14:52:02 +01:00 |
|
Florent Kermarrec
|
6bdf60567c
|
liteeth/mac/core: fix hw_preamble_crc register generation
|
2015-03-19 13:03:27 +01:00 |
|
Florent Kermarrec
|
236ea0f572
|
liteeth: use bios ip_address in example designs
|
2015-03-18 18:18:43 +01:00 |
|
Florent Kermarrec
|
a266deb58e
|
LiteXXX cores: fix frequency print in test/test_regs.py
|
2015-03-17 16:01:25 +01:00 |
|
Florent Kermarrec
|
d2cb41bc63
|
LiteXXX cores: convert port parameter to int if is digit in test/make.py
|
2015-03-17 15:58:21 +01:00 |
|
Florent Kermarrec
|
2327710387
|
liteeth/phy/gmii : set tx_er to 0 only if it exits
|
2015-03-17 12:24:06 +01:00 |
|
Florent Kermarrec
|
408d0fd2dd
|
liteeth: use default programmer in make.py
|
2015-03-17 12:12:21 +01:00 |
|
Florent Kermarrec
|
ec6ae75065
|
liteeth: use CRG from Migen in base example
|
2015-03-17 12:11:51 +01:00 |
|
Florent Kermarrec
|
faf185d58d
|
liteeth: make gmii phy generic
|
2015-03-16 23:04:37 +01:00 |
|
Florent Kermarrec
|
c3c7f627d9
|
liteeth/phy: typo (thanks sb)
|
2015-03-12 21:54:10 +01:00 |
|
Florent Kermarrec
|
767d45727a
|
uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty).
|
2015-03-12 16:57:38 +01:00 |
|
Florent Kermarrec
|
b157031e8a
|
uart/sim: add pty (optional, to use flterm)
|
2015-03-09 23:29:06 +01:00 |
|
Florent Kermarrec
|
6cbf13036b
|
liteeth/mac: fix padding limit (+1), netboot OK with sim platform
|
2015-03-09 20:59:34 +01:00 |
|
Florent Kermarrec
|
47cceea222
|
liteeth/mac: use Counter in sram and move some logic outside of fsms
|
2015-03-09 20:22:14 +01:00 |
|
Florent Kermarrec
|
b10836a8eb
|
liteeth/phy/sim: create ethernet tap in __init__ and destroy it in do_exit
|
2015-03-09 17:21:29 +01:00 |
|
Florent Kermarrec
|
360c849f21
|
liteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter)
|
2015-03-09 13:23:39 +01:00 |
|
Florent Kermarrec
|
5dbd8af4be
|
liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ethernet tap
|
2015-03-09 13:23:37 +01:00 |
|
Florent Kermarrec
|
d20b9c2221
|
uart: pass *args, **kwargs to sim phy
|
2015-03-06 12:08:10 +01:00 |
|
Florent Kermarrec
|
af66ca7bad
|
uart: add phy autodetect function
|
2015-03-06 10:19:29 +01:00 |
|
Florent Kermarrec
|
95fa753149
|
liteeth: add phy autodetect function (phy can still be instanciated directly)
|
2015-03-06 10:10:34 +01:00 |
|
Florent Kermarrec
|
52f1c45407
|
LiteXXX cores: fix test_reg.py
|
2015-03-04 23:13:14 +01:00 |
|
Florent Kermarrec
|
200791c81d
|
uart: generate ack for rx (serialboot OK with sim)
|
2015-03-04 00:57:37 +01:00 |
|
Florent Kermarrec
|
7c058a52c9
|
com/spi: use .format in tb
|
2015-03-03 10:44:05 +01:00 |
|
Florent Kermarrec
|
1d4dc45436
|
LiteXXX cores: use format in prints
|
2015-03-03 10:29:28 +01:00 |
|
Florent Kermarrec
|
b305b7828a
|
sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it
|
2015-03-02 08:36:39 +01:00 |
|
Florent Kermarrec
|
f58394f6af
|
soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
|
2015-03-01 18:25:47 +01:00 |
|
Florent Kermarrec
|
096e95cb59
|
uart: use data instead of d on endpoint's layouts (coherency with others cores)
|
2015-03-01 16:56:48 +01:00 |
|
Florent Kermarrec
|
1e6d1deae8
|
uart: add sim phy
|
2015-03-01 16:52:50 +01:00 |
|
Florent Kermarrec
|
649cdeb265
|
liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
|
2015-03-01 16:48:41 +01:00 |
|
Florent Kermarrec
|
bd4d3cd73b
|
uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
|
2015-03-01 12:14:34 +01:00 |
|
Florent Kermarrec
|
c21a7956c8
|
liteXXX cores: remove Identifier duplication
|
2015-03-01 11:24:58 +01:00 |
|
Florent Kermarrec
|
67ca0da1d9
|
liteXXX cores: share same methodology for on-board tests
|
2015-03-01 11:21:12 +01:00 |
|
Florent Kermarrec
|
b32a0e6f9e
|
liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins
|
2015-02-28 23:33:00 +01:00 |
|
Florent Kermarrec
|
b34be816ec
|
liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH)
|
2015-02-28 22:23:48 +01:00 |
|
Florent Kermarrec
|
5c43d4d091
|
litescope: create example design derived from SoC that can be used on all targets
|
2015-02-28 22:19:24 +01:00 |
|
Florent Kermarrec
|
0fd1b9df8d
|
liteXXX cores: remove redefinition of get_csr_csv
|
2015-02-28 21:45:05 +01:00 |
|
Florent Kermarrec
|
5bd1ab7fa1
|
liteXXX cores: update README and doc
|
2015-02-28 21:40:59 +01:00 |
|
Florent Kermarrec
|
69e869893d
|
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
|
2015-02-28 11:36:15 +01:00 |
|
Florent Kermarrec
|
912573f5c9
|
liteusb: move files and modify import to misoclib.com.liteusb
|
2015-02-28 11:18:00 +01:00 |
|
Florent Kermarrec
|
b647fe5823
|
merge liteusb
|
2015-02-28 11:16:16 +01:00 |
|
Florent Kermarrec
|
2c3e8a2804
|
liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)
|
2015-02-28 11:04:48 +01:00 |
|
Florent Kermarrec
|
df0ba1b03c
|
litescope: create example_designs directory
|
2015-02-28 10:42:12 +01:00 |
|
Florent Kermarrec
|
c4ebf244a1
|
litescope: move files and modify import to misoclib.tools.litescope
|
2015-02-28 10:33:46 +01:00 |
|
Florent Kermarrec
|
a43c555ee3
|
misoclib/com: add spi (only SPIMaster for now)
|
2015-02-28 09:43:03 +01:00 |
|
Florent Kermarrec
|
2c51adcd68
|
misoclib: better organization (create cores categories: cpu, mem, com, ...)
|
2015-02-28 09:40:44 +01:00 |