8c80a6c19c
linux dts: rework "rocket" in cpu_name into cpu_name == "rocket"
2024-06-11 13:08:25 +02:00
87ae5db16b
linux dts: add vexii clint support
2024-06-10 18:10:13 +02:00
f0b0d8db29
linux dts: add vexii clint support
2024-06-10 17:02:00 +02:00
9c202b59d1
Fix axi id width
2024-06-07 18:33:05 +02:00
bd96b47041
Vexii fix mem data width
2024-06-06 16:36:56 +02:00
0e04949485
vexii fix l1 cache size
2024-06-06 13:50:27 +02:00
9165886525
snyc
2024-05-28 12:59:27 +02:00
2dac84f32c
vexii l2 now support self flush. ex :
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--l2-self-flush=40c00000,40DD4C00,1666666
2024-05-27 17:37:30 +02:00
4a6efa47c1
Add variants to VexiiRiscv
2024-05-23 16:44:20 +02:00
06bbbe78e4
vexii/naxii fix floating axi wires
2024-05-20 08:56:38 +02:00
21e0ec7f98
vexii/naxii fix floating axi wires
2024-05-20 08:55:05 +02:00
5eeb999694
update vexii
2024-05-18 16:59:27 +02:00
8c0f5447ed
fix nax/vexii git checkout process, thanks JoyBed
2024-05-18 10:01:29 +02:00
0720ffb404
Update vexii
2024-05-17 10:00:24 +02:00
122e060a5e
update vexii
2024-05-16 19:30:15 +02:00
60b0273eda
Add baremetal IRQ support
2024-05-16 18:58:16 +02:00
57f74da8d8
Merge branch 'master' into vexiiriscv
2024-05-16 16:17:21 +02:00
d7b4c7bc9c
Merge pull request #1954 from enjoy-digital/vexriscv_smp_irqs
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Add baremetal IRQ support to VexRiscv-SMP and NaxRiscv.
2024-05-16 10:55:12 +02:00
fbf03ec74c
inteconnect/axi_lite/wishbone SRAM: Switch back to LiteXModule and add autocsr_exclude on mem to avoid AutoCSR to collect it.
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Also cleanup self.mem.get_port call.
2024-05-16 10:36:44 +02:00
c0d9224f09
integration/export/_generate_csr_header_includes_c: Fix refactoring issue and do not include generated/soc.h when access functions are disabled.
2024-05-16 09:19:18 +02:00
d4c1a10817
cores/cpu/naxriscv: Add baremetal IRQ support
2024-05-14 14:57:29 +02:00
e03b097e8e
software/libbase/isr.c: Simplify using __riscv_plic__ define.
2024-05-14 14:47:01 +02:00
c79e1ef95f
cores/cpu/vexriscv_smp: Remove FIXME/CHECKME now that working and remove UART_POLLING flag.
2024-05-14 14:43:57 +02:00
786c929f08
cores/cpu/vexriscv_smp: fix PLIC_EXT_IRQ_BASE
2024-05-14 14:24:37 +02:00
8a83585b85
Merge pull request #1953 from enjoy-digital/export_csr_c_rework
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Simplify/Cleanup C exports and disable Fields accessors generation by default.
2024-05-14 12:54:48 +02:00
8eaa53ae9a
test/test_cpu: Disable cv32e40p test (need to update/wait for pythondata to be updated).
2024-05-14 12:53:09 +02:00
c810b89464
Merge pull request #1951 from nuntipat/update-cv32e40p
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Update CV32E40P to be based on the OpenHW Group's repo
2024-05-14 12:11:50 +02:00
9b6e231a1a
Merge pull request #1952 from nuntipat/fix-csr-def-cv32e41p
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Fix CSR register definition for the CV32E41P core
2024-05-14 12:08:42 +02:00
46911d5078
soc/integration/builder: Disable fields_access_functions generation by default since not widely used (at least not in LiteX "official" projects).
2024-05-14 11:59:13 +02:00
2574cc1ddc
integration/export: Fix read_function refactoring.
2024-05-14 11:55:34 +02:00
7b7334fc17
cpu/vexiiriscv update
2024-05-14 11:41:21 +02:00
29bb397bb6
soc/integration/export: Add parameter to enable/disable fields access function generation.
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Fields access function have been contributed and probably used by a few project but not really
by LiteX projects or cores itselves.
This generates complex code and compilation warnings, so it can be useful to disable them by default (but still allow used to enable them).
2024-05-14 11:22:46 +02:00
9f4bd5cec8
integration/export: Split get_csr_header in simpler functions.
2024-05-14 11:00:41 +02:00
c42cc350c6
integration/export: Split _get_rw_functions_c in simpler functions.
2024-05-14 10:47:38 +02:00
3506a5e82d
cores/cpu/vexriscv_smp: Prepare IRQ support based on Rocket IRQ support (not yet working).
2024-05-14 10:04:13 +02:00
49897ee018
software/libbase/isr.c: Cleanup plic_init/isr and move PLIC_EXT_IRQ_BASE to cores/cpu/../irq.h since specific to each CPU.
2024-05-14 10:02:56 +02:00
b0acf6136e
Fix CSR register definition for the CV32E41P core
2024-05-13 20:03:16 -04:00
41564cc47b
Update CV32E40P to be based on the OpenHW Group's repo
2024-05-13 19:59:42 -04:00
2613ae606a
interconnect/packet/Status: Simplify logic.
2024-05-13 17:52:24 +02:00
8b175c2575
CHANGES: Update.
2024-05-13 16:33:11 +02:00
0d3a8220dd
Merge pull request #1948 from Liamolucko/riscv-triples
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Add missing 32-bit variants of RISC-V target triples
2024-05-07 15:15:09 +02:00
b61e8b5d42
Merge pull request #1945 from Nicolas-Gaudin/master
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Support isr for cv32e41p core
2024-05-07 15:13:44 +02:00
e4cfe87109
Merge pull request #1946 from nrndda/AXILite_LitexXModule_revert
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Revert LitexModule for AXILiteSRAM as well.
2024-05-07 15:10:55 +02:00
588b7a9519
Update Vexii
2024-05-06 19:48:56 +02:00
86a43c9ff7
integration/export: Fix get_csr_header/base_define when with_csr_base_define is set to False.
2024-05-06 14:59:17 +02:00
e07c4fdb2a
Add missing 32-bit variants of RISC-V target triples
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I had to waste another 10-15 minutes building a `riscv64-none-elf` GCC
instead after LiteX didn't like my `riscv32-none-elf` one, so I thought
I'd quickly add it. (I was using that target triple because it's what
Nix's `pkgsCross.riscv32-embedded` package set uses).
I also added 32-bit variants of the rest of the target triples which
didn't have them.
2024-05-04 17:41:32 +10:00
26f5e8a149
Revert LitexModule for AXILiteSRAM as well. Follows revert d021564fca for wishbobe.
2024-05-03 00:51:01 +03:00
bd0adb5be7
Support isr for cv32e41p core
2024-04-30 14:07:07 +02:00
76a704377f
Merge pull request #1941 from motec-research/vexriscv_debug_halted
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cpu/vexriscv: expose o_halted
2024-04-26 13:43:40 +02:00
7aae2bf897
Merge pull request #1940 from enjoy-digital/Dolu1990-patch-1
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cpu/naxriscv update mBus to preserve memory accesses offset
2024-04-26 11:21:18 +02:00
Dolu1990
enjoy-digital
Nuntipat Narkthong
Liam Murphy
Dmitry Derevyanko
Nicolas Gaudin