9d08c65e8a
build/generic_platform: Make sure default_clk_period constraint is only applied when default_clk_period exists.
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In simulation, default_clk_period is not necessarily required.
2021-03-10 12:25:35 +01:00
ee2d373477
Merge pull request #843 from gregdavill/monitor_token_fix
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cores/stream/monitor: Fix typo
2021-03-10 11:00:55 +01:00
e48b269d77
build/generic_platform: Fix use_default_clk set when not user provided sys_clk.
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Prevented the default timing constraint to be generated in the timing constraint file.
2021-03-10 10:47:22 +01:00
31cc7f1e42
cores/stream/monitor: Fix typo
2021-03-10 09:11:07 +10:30
0e7d8219ea
soc/cores/gpio: Simplify GPIOIn IRQ, make polarity configurable and also add optional IRQ to GPIOTristate.
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Ex of instance:
from litex.soc.cores import gpio
gpio_in_pads = Signal(16)
self.submodules.gpio_in = gpio.GPIOIn(gpio_in_pads, with_irq=True)
self.add_csr("gpio_in")
2021-03-09 13:57:48 +01:00
0d8b6f8fbb
csr_eventmanager/EventSourceProcess: Add Rising Edge support and Falling/Rising selection.
2021-03-09 13:55:43 +01:00
ece9005949
cpu/vexriscv/core: Rename timer_enabled parameter to with_timer (for consistency with codebase) and disable timer by default (since increasing resources and causing issue on some iCE40 designs).
2021-03-09 09:07:52 +01:00
834c90b71f
Merge pull request #841 from gatecat/radiant_pins_x
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build/radiant: Skip location constraint for X pins
2021-03-08 16:30:22 +01:00
c64e2d3a85
build/radiant: Skip location constraint for X pins
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-08 14:27:32 +00:00
5af8e5c934
soc/add_etherbone: Fix UDPIPCore clock domain (should still run at eth_clk even if Etherbone is running in sys_clk) since data-width convertion is done on UDP.
2021-03-08 13:50:22 +01:00
6bb0541f9a
Remove ussysmon.py as it is consolidated inside xadc.py
2021-03-06 14:31:24 -08:00
a1e54671be
sim/serial2console: Remove \r workaround since no longer required and generating double carrier return in simulation.
2021-03-06 17:36:21 +01:00
7e3912aaef
software/demo: Make hellocpp optional (only build with --with-cxx) to avoid adding g++ as a dependency for an optional feature.
2021-03-06 17:31:07 +01:00
647d3eb51a
soc/cores/xadc.py: Move ussysmon here
2021-03-06 08:14:13 -08:00
31ac6659c9
cores/video: Add VideoS7HDMIPHY for Xilinx 7-Series.
2021-03-05 14:30:28 +01:00
9624cce188
cores/video: Mode VideoVGAPHY/VideoDVIPHY and add separators.
2021-03-05 14:27:08 +01:00
0280a9dd57
soc/add_video_framebuffer: Pass clock_domain to VideoFrameBuffer.
2021-03-05 14:23:39 +01:00
8b531b4215
cores: Add code_tmds with TMDS Encoder from Mixxeo/LiteVideo.
2021-03-04 19:32:41 +01:00
10d87e4138
cores/video/VideoPHYs: Use IO primitives.
2021-03-04 18:22:34 +01:00
82d0ecd7bd
cores/video/VideoTerminal: Add CLEAR-XY after reset.
2021-03-04 17:55:37 +01:00
a1e7aab35c
cores/clock/xilinx_usp/USPIDELAYCTRL: Apply USIDELAYCTRL's changes.
2021-03-04 14:42:50 +01:00
60e2d3335f
cores/clock/xilinx_us: Remove USP modules (refactoring issue).
2021-03-04 14:42:03 +01:00
2d5b4b206b
bios: Add VideoFrameBuffer VTG/DMA initialisation.
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This just configures the enables for now since other parameters are pre-configured
during the build.
2021-03-04 12:01:32 +01:00
f553b5fc83
soc/cores/video: Improve/Cleanup VideoFrameBuffer, disable by default and modify default hres/vres to 800/600.
2021-03-04 11:59:44 +01:00
0ee92448b9
soc/cores/dma: Add default parameters to add_csr (similar to LiteDRAMDMAs), minor cosmetic cleanups and also add offset CSRStatus on WishboneDMAWriter (for symetry with WishboneDMAReader).
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Defaults parameters can allow the FPGA gateware to behave by itself after initialization while still being configurable by software.
2021-03-04 11:53:43 +01:00
225a518f7e
soc/cores/video: Move LiteDRAMDMAReader import to VideoFramerBuffer to avoid LiteDRAM dependency.
2021-03-04 08:40:47 +01:00
ae5f67f6f0
litex/soc/cores/ussysmon.py: minor bug
2021-03-03 14:47:52 -08:00
1793efb50b
litex/soc/cores/ussysmon.py: dadr address space bump
2021-03-03 14:38:27 -08:00
ccc8916995
soc/cores/video: Add initial (and simple) VideoFrameBuffer core.
2021-03-03 19:58:11 +01:00
922f85e64b
litex/soc/cores/ussysmon.py: ADC transfer function
2021-03-03 10:50:58 -08:00
24fb153fa1
soc/integration: Add add_video_terminal method to LiteXSoC.
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Adds the new LiteX's VideoTerminal core to the SoC:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
2021-03-03 17:45:02 +01:00
35ffba8801
soc/cores: Add simple VideoOut core with VideoTimingGenerator, Video Patterns, VideoTerminal, VideoDVIPHY and VideoVGAPHY.
2021-03-03 16:17:12 +01:00
c5ee6741a0
software/liblitedram: Use new DQS delay reset procedure on Ultrascale(+) (by increments).
2021-03-03 11:32:43 +01:00
d3407c67b1
build/sim/core: Cast main_time to vluint64_t to avoid ambiguity error of the dump function to be used.
2021-03-03 09:25:54 +01:00
134c628357
cores/spi_flash: Minor cosmetic cleanups, SpiFlashQuadReadWrite has also been moved to the end with a Note since should probably be re-factored.
2021-03-03 09:15:51 +01:00
61dcd1e8fd
soc/cores/led: Minor cosmetic cleanups.
2021-03-03 09:02:41 +01:00
19b1e50cbd
soc/cores/icap: Minor cosmetic cleanups.
2021-03-03 09:01:41 +01:00
e6f1d677e7
soc/cores/freqmeter: Minor cosmetic cleanups.
2021-03-03 08:59:51 +01:00
ce5e3e3b93
soc/cores/ecc: Minor cosmetic cleanups.
2021-03-03 08:55:37 +01:00
2fd7451fc9
soc/cores/code_8b10b: Minor cosmetic cleanups.
2021-03-03 08:54:31 +01:00
2e531e0ec7
soc/cores/dna: Add separator/comment.
2021-03-03 08:49:47 +01:00
71f7ce6a57
soc/cores/ussysmon.py: Xilinx XADC like thingy for UltraScale devices
2021-03-02 20:31:52 -08:00
c23e8813fc
Merge pull request #836 from hplp/master
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demo with c++ HW example
2021-03-02 09:13:10 +01:00
7fd39235af
Merge pull request #1 from hplp/cppdemo
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demo with basic C and C++ examples
2021-03-02 01:31:46 -05:00
769f36d468
extend demo with basic C and C++ examples
2021-03-02 01:28:21 -05:00
415bf63594
Merge pull request #830 from dayjaby/vexriscv_mem_map
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VexRiscv: More general mem_map
2021-03-01 11:15:56 +01:00
ceb8a6502c
VexRiscv: More general mem_map
2021-02-25 10:36:43 +01:00
6e883b4513
tools/litex_sim: Add boot to main_ram when sdram_init contents provided.
2021-02-25 09:10:26 +01:00
8f5d2ba27f
tools/litex_sim: Disable SDRAM memtest when sdram_init contents provided.
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This avoid corrupting pre-initialized contents or disabling memtest manually.
2021-02-25 09:06:26 +01:00
80bd4ac4ec
bios: Add boot command to be able to boot directly from system memory.
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This is useful for un-usual boot sequences where the binaries are not
loaded directly by the BIOS but externally (over a bridge for example).
Example of use:
$litex_sim
$litex_bare_metal_demo --build-path=build/sim
$litex_sim --ram-init=demo.bin
Press Esc during the LiteX boot.
litex> help
LiteX BIOS, available commands:
flush_cpu_dcache - Flush CPU data cache
crc - Compute CRC32 of a part of the address space
ident - Identifier of the system
help - Print this help
serialboot - Boot from Serial (SFL)
romboot - Boot from ROM
reboot - Reboot
boot - Boot from Memory
mem_speed - Test memory speed
mem_test - Test memory access
mem_copy - Copy address space
mem_write - Write address space
mem_read - Read address space
mem_list - List available memory regions
litex>
litex> mem_list
Available memory regions:
ROM 0x00000000 0x8000
SRAM 0x01000000 0x2000
MAIN_RAM 0x40000000 0x10000000
CSR 0x82000000 0x10000
litex>
litex> boot 0x40000000
Executing booted program at 0x40000000
--============= Liftoff! ===============--
LiteX minimal demo app built Feb 24 2021 11:30:05
Available commands:
help - Show this command
reboot - Reboot CPU
donut - Spinning Donut demo
litex-demo-app>
2021-02-24 11:41:01 +01:00
Florent Kermarrec
Greg Davill
gatecat
Vamsi Vytla
Sergiu Mosanu
David Jablonski