dac10f5570
bus/wb2lasmi: use existing interface to determine WB width to be consistent with other modules
2013-08-26 20:33:34 +02:00
2cf6b6c768
wishbone/SRAM: fix non-32-bit bus
2013-08-26 20:32:59 +02:00
33ca4d778f
wishbone2lasmi: configurable data width
2013-08-26 20:29:12 +02:00
628fa8ce9e
wishbone : add DownConverter
2013-08-26 20:28:09 +02:00
a653a6144b
wishbone2lasmi : add support for 32 bits lasmim data width
2013-08-20 18:49:46 +02:00
246b860a85
csr: new data width API
2013-07-28 16:33:36 +02:00
6ba0d4bd0d
bus/wishbone: configurable data width
2013-07-27 22:25:07 +02:00
f62eff0309
bus/csr/Initiator: correct read latency
2013-07-27 15:37:47 +02:00
fe18397acc
wishbone.py: add Crossbar (concurrent/parallel/many-to-many interconnect)
2013-07-22 10:30:44 +02:00
5b36f688ea
Remove ASMI
2013-07-16 18:50:50 +02:00
b016a60b85
lasmibus: fix master locking
2013-07-15 21:45:07 +02:00
f5ddd33e7e
dfi: split phase description
2013-07-10 19:56:47 +02:00
43fe16ef73
bus/lasmibus: add separate req/data ack to target and initiator
2013-07-10 19:09:51 +02:00
7e6fbd31a4
lasmibus/crossbar: simplify master ack generation
2013-07-07 18:56:43 +02:00
d0caa738bd
FSM: new API
2013-06-25 22:17:39 +02:00
d6f7b4cee6
lasmi: separate request and data ack to support bankmachine FIFOs (buggy/incomplete)
2013-06-17 23:36:03 +02:00
6d6d232cad
lasmibus/crossbar: better switching policy
2013-06-15 16:51:09 +02:00
ac2cde0e87
asmibus: remove port sharing
2013-06-14 18:34:36 +02:00
0c52c08989
bus/asmibus: fix slot aging timer
2013-06-14 17:57:43 +02:00
1ec1fb9ebe
bus/lasmibus/Crossbar: support cba_shift=0
2013-06-11 18:15:49 +02:00
fe54c68762
lasmi: fix minor problems
2013-06-10 22:49:33 +02:00
932bfa7e75
bus: Wishbone -> LASMI bridge (untested)
2013-06-10 18:52:07 +02:00
f2e2397c9d
bus/lasmibus: bugfixes
2013-06-09 23:36:32 +02:00
a836cba790
bus/lasmibus: add target and initiator
2013-06-09 16:03:22 +02:00
35f9f2e9d7
bus/lasmi: interface definition and crossbar (untested)
2013-06-08 15:49:50 +02:00
85813b3b58
csr/sram: fix reads on high addresses when word_bits != 0
2013-06-03 21:52:23 +02:00
e5e3492afe
csr/sram: fix page_bits computation
2013-06-03 21:51:44 +02:00
ebbd5ebcd2
bus/csr/SRAM: better handling of writes to memories larger than the CSR width
2013-05-30 18:45:04 +02:00
bac62a32a9
Make memory ports part of specials
...
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
70ffe86356
New migen.fhdl.std to simplify imports + len->flen
2013-05-22 17:11:09 +02:00
5208baada8
bus/wishbone/SRAM: support init and read_only
2013-05-19 20:53:54 +02:00
7ada0159fd
bus/csr/SRAM: support init
2013-05-19 20:53:37 +02:00
792b8fed1b
bus/asmi: port sharing support
2013-05-12 15:58:39 +02:00
8e11fcf1d0
bus/csr/SRAM: fix Module conversion errors
2013-04-14 13:55:04 +02:00
29b468529f
bus: replace simple bus module with new bidirectional Record
2013-04-01 21:54:21 +02:00
c4f4143591
New CSR API
2013-03-30 17:28:41 +01:00
51bec340ab
sim: remove PureSimulable (superseded by Module)
2013-03-15 19:41:30 +01:00
04df076fba
bank: automatic register naming
2013-03-12 15:45:24 +01:00
80970b203c
bus/asmibus: use implicit finalization
2013-03-11 17:11:59 +01:00
174e8cb8d6
bus/asmibus: use fhdl.module API
2013-03-10 19:28:22 +01:00
2b8dc52c13
Use common definition for FinalizeError
2013-03-09 19:03:13 +01:00
b75fb7f97c
csr/SRAM: support for writes with memory widths larger than bus words
2013-03-09 00:50:57 +01:00
9b4ca987e0
bus/csr: support memories with larger word width than the bus (read only)
2013-03-03 19:27:13 +01:00
d2491828a4
csr/SRAM: prefix page register with memory name
2013-03-01 12:06:12 +01:00
f9acee4e68
corelogic -> genlib
2013-02-22 23:19:37 +01:00
49cfba50fa
New 'specials' API
2013-02-22 17:56:35 +01:00
3fae6c8f03
Do not use super()
2012-12-18 14:54:33 +01:00
280a87ea69
elsewhere: do not create interface in default param
2012-12-06 17:34:48 +01:00
c3fdf42825
bus/csr: add SRAM
2012-12-06 17:16:17 +01:00
4bcb39699b
bus/wishbone/sram: accept memories < 32 bits
2012-12-01 13:04:22 +01:00
Sebastien Bourdeauducq
Florent Kermarrec
Robert Jördens
Kenneth Ryerson