4d7a7f5ba1
Merge pull request #1742 from Icenowy/gwddrfix
...
build/gowin/common: Fix DDRInput
2023-08-16 08:01:29 +02:00
c1d8db396d
build/gowin/common: Fix DDRInput
...
The DDRInput of Gowin seems to be never used and contains a typo that
prevents it from being really used.
Fix this typo.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-11 14:56:56 +08:00
577674bff2
test: Add minimal test_spi_mmap with simulation of SPIMaster.
2023-08-04 17:51:22 +02:00
688dae0112
cores/spi: Add new SPIMMAP core allowing doing SPI accesses directly from MMAP.
...
Implements a new SPIMMAP module, allowing accessing multiple SPI peripherals directly
from MMAP. It allows configurable SPI transactions: mode, bit order, and data width.
Developed and funded through a collaboration with MoTeC.
Example of integration:
# SPI MMAP ---------------------------------------------------------------------------------
spi_pads = Record([("clk", 1), ("cs_n", 8), ("mosi", 1), ("miso", 1)])
spi_mmap_tx_region = SoCRegion(origin=0x8000_0000, size=4096, cached=False)
spi_mmap_rx_region = SoCRegion(origin=0x8000_1000, size=4096, cached=False)
self.spi_mmap = SPIMMAP(
pads = spi_pads,
data_width = 32,
sys_clk_freq = sys_clk_freq,
tx_origin = spi_mmap_tx_region.origin,
rx_origin = spi_mmap_rx_region.origin,
tx_fifo_depth = 32,
rx_fifo_depth = 32,
)
self.bus.add_slave(name="spi_tx",
slave = self.spi_mmap.tx_mmap.bus,
region = spi_mmap_tx_region,
)
self.bus.add_slave(name="spi_rx",
slave = self.spi_mmap.rx_mmap.bus,
region = spi_mmap_rx_region,
)
self.irq.add("spi_mmap", use_loc_if_exists=True)
Example of use from CPU C firmware:
/* SPI TX Offsets */
#define SPI_TX_CTRL_ENABLE (1 << 0)
#define SPI_TX_CTRL_THRESHOLD (1 << 16)
#define SPI_TX_STAT_ONGOING (1 << 0)
#define SPI_TX_STAT_EMPTY (1 << 1)
#define SPI_TX_STAT_FULL (1 << 2)
#define SPI_TX_STAT_LEVEL (1 << 16)
/* SPI RX Offsets */
#define SPI_RX_CTRL_ENABLE (1 << 0)
#define SPI_RX_CTRL_THRESHOLD (1 << 16)
#define SPI_RX_STAT_ONGOING (1 << 0)
#define SPI_RX_STAT_EMPTY (1 << 1)
#define SPI_RX_STAT_FULL (1 << 2)
#define SPI_RX_STAT_LEVEL (1 << 16)
/* SPI TX/RX Engine */
#define SPI_TX_RX_ENGINE_ENABLE (1 << 0)
/* SPI SLOT Offsets */
#define SPI_SLOT_ENABLE (1 << 0)
#define SPI_SLOT_MODE (1 << 1)
#define SPI_SLOT_LENGTH (1 << 3)
#define SPI_SLOT_BITORDER (1 << 5)
#define SPI_SLOT_LOOPBACK (1 << 6)
#define SPI_SLOT_DIVIDER (1 << 16)
/* SPI SLOT Values */
#define SPI_SLOT_MODE_0 0b00
#define SPI_SLOT_MODE_3 0b11
#define SPI_SLOT_LENGTH_32B 0b00
#define SPI_SLOT_LENGTH_16B 0b01
#define SPI_SLOT_LENGTH_8B 0b10
#define SPI_SLOT_BITORDER_MSB_FIRST 0b0
#define SPI_SLOT_BITORDER_LSB_FIRST 0b1
#define SPI_SLOT_EV_TX (1 << 0)
#define SPI_SLOT_EV_RX (1 << 1)
/* Test SPI with various length (BE) */
void test_spi_length_8_16_32(void) {
volatile unsigned char *spi_tx_8 = (unsigned char *)SPI_TX_BASE;
volatile unsigned short *spi_tx_16 = (unsigned short *)SPI_TX_BASE;
volatile unsigned int *spi_tx_32 = (unsigned int *)SPI_TX_BASE;
volatile unsigned char *spi_rx_8 = (unsigned char *)SPI_RX_BASE;
volatile unsigned short *spi_rx_16 = (unsigned short *)SPI_RX_BASE;
volatile unsigned int *spi_rx_32 = (unsigned int *)SPI_RX_BASE;
int errors = 0;
printf("Test SPI with various length (BE): 8, 16 and 32-bit...\n");
/* Configure Slots */
spi_mmap_ctrl_slot_control0_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_0 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
4 * SPI_SLOT_DIVIDER
);
spi_mmap_ctrl_slot_control1_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_0 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
4 * SPI_SLOT_DIVIDER
);
spi_mmap_ctrl_slot_control2_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_0 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
4 * SPI_SLOT_DIVIDER
);
spi_mmap_ctrl_slot_control3_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_0 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
4 * SPI_SLOT_DIVIDER
);
/* Enable SPI Engine */
spi_mmap_tx_rx_engine_control_write(1 * SPI_TX_RX_ENGINE_ENABLE);
/* TX 8-bit transfers */
spi_tx_8[0] = 0x5a;
spi_tx_8[4] = 0x01;
spi_tx_8[8] = 0x5a;
spi_tx_8[12] = 0x01;
/* TX 16-bit transfers */
spi_tx_16[0] = 0x5aa5;
spi_tx_16[2] = 0x0102;
spi_tx_16[4] = 0x5aa5;
spi_tx_16[6] = 0x0102;
/* TX 32-bit transfers */
spi_tx_32[0] = 0x5aa55aa5;
spi_tx_32[1] = 0x01020304;
spi_tx_32[2] = 0x5aa55aa5;
spi_tx_32[3] = 0x01020304;
/* Small delay */
busy_wait(1);
/* Read RX 8-bit transfers */
if (spi_rx_8[ 0] != 0x5a)
errors++;
if (spi_rx_8[ 4] != 0x01)
errors++;
if (spi_rx_8[ 8] != 0x5a)
errors++;
if (spi_rx_8[12] != 0x01)
errors++;
/* Read RX 16-bit transfers */
if (spi_rx_16[0] != 0x5aa5)
errors++;
if (spi_rx_16[2] != 0x0102)
errors++;
if (spi_rx_16[4] != 0x5aa5)
errors++;
if (spi_rx_16[6] != 0x0102)
errors++;
/* Read RX 32-bit tranfers */
if (spi_rx_32[0] != 0x5aa55aa5)
errors++;
if (spi_rx_32[1] != 0x01020304)
errors++;
if (spi_rx_32[2] != 0x5aa55aa5)
errors++;
if (spi_rx_32[3] != 0x01020304)
errors++;
/* Disable SPI Engine */
spi_mmap_tx_rx_engine_control_write(0 * SPI_TX_RX_ENGINE_ENABLE);
/* Result */
printf("errors: %d\n", errors);
}
/* Test SPI with various clk divider */
void test_spi_clk_divider(void) {
volatile unsigned int *spi_tx_32 = (unsigned int *)SPI_TX_BASE;
volatile unsigned int *spi_rx_32 = (unsigned int *)SPI_RX_BASE;
int errors = 0;
printf("Test SPI with various clk divider: 4, 8, 16 and 32...\n");
/* Configure Slots */
spi_mmap_ctrl_slot_control0_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_0 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
4 * SPI_SLOT_DIVIDER
);
spi_mmap_ctrl_slot_control1_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_0 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
8 * SPI_SLOT_DIVIDER
);
spi_mmap_ctrl_slot_control2_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_0 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
16 * SPI_SLOT_DIVIDER
);
spi_mmap_ctrl_slot_control3_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_0 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
32 * SPI_SLOT_DIVIDER
);
/* Enable SPI Engine */
spi_mmap_tx_rx_engine_control_write(1 * SPI_TX_RX_ENGINE_ENABLE);
/* TX 32-bit transfers */
spi_tx_32[0] = 0x01020304;
spi_tx_32[1] = 0x5aa55aa5;
spi_tx_32[2] = 0x01020304;
spi_tx_32[3] = 0x5aa55aa5;
/* Small delay */
busy_wait(1);
/* Read RX 32-bit tranfers */
if (spi_rx_32[0] != 0x01020304)
errors++;
if (spi_rx_32[1] != 0x5aa55aa5)
errors++;
if (spi_rx_32[2] != 0x01020304)
errors++;
if (spi_rx_32[3] != 0x5aa55aa5)
errors++;
/* Disable SPI Engine */
spi_mmap_tx_rx_engine_control_write(0 * SPI_TX_RX_ENGINE_ENABLE);
/* Result */
printf("errors: %d\n", errors);
}
/* Test SPI with various SPI modes */
void test_spi_modes(void) {
volatile unsigned int *spi_tx_32 = (unsigned int *)SPI_TX_BASE;
volatile unsigned int *spi_rx_32 = (unsigned int *)SPI_RX_BASE;
int errors = 0;
printf("Test SPI with various SPI modes: 0 and 3...\n");
/* Configure Slots */
spi_mmap_ctrl_slot_control0_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_0 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
4 * SPI_SLOT_DIVIDER
);
spi_mmap_ctrl_slot_control1_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_3 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
4 * SPI_SLOT_DIVIDER
);
/* Enable SPI Engine */
spi_mmap_tx_rx_engine_control_write(1 * SPI_TX_RX_ENGINE_ENABLE);
/* TX 32-bit transfers */
spi_tx_32[0] = 0x5aa55aa5;
spi_tx_32[1] = 0x5aa55aa5;
/* Small delay */
busy_wait(1);
/* Read RX 32-bit tranfers */
if (spi_rx_32[0] != 0x5aa55aa5)
errors++;
if (spi_rx_32[1] != 0x5aa55aa5)
errors++;
/* Disable SPI Engine */
spi_mmap_tx_rx_engine_control_write(0 * SPI_TX_RX_ENGINE_ENABLE);
/* Result */
printf("errors: %d\n", errors);
}
/* Test SPI with various bitorders */
void test_spi_bitorders(void) {
volatile unsigned int *spi_tx_32 = (unsigned int *)SPI_TX_BASE;
volatile unsigned int *spi_rx_32 = (unsigned int *)SPI_RX_BASE;
int errors = 0;
printf("Test SPI with various bitorders: MSB and LSB first...\n");
/* Configure Slots */
spi_mmap_ctrl_slot_control0_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_0 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
4 * SPI_SLOT_DIVIDER
);
spi_mmap_ctrl_slot_control1_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_0 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_LSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
4 * SPI_SLOT_DIVIDER
);
/* Enable SPI Engine */
spi_mmap_tx_rx_engine_control_write(1 * SPI_TX_RX_ENGINE_ENABLE);
/* TX 32-bit transfers */
spi_tx_32[0] = 0xff000000;
spi_tx_32[1] = 0xff000000;
/* Small delay */
busy_wait(1);
/* Read RX 32-bit tranfers */
if (spi_rx_32[0] != 0xff000000)
errors++;
if (spi_rx_32[1] != 0xff000000)
errors++;
/* Disable SPI Engine */
spi_mmap_tx_rx_engine_control_write(0 * SPI_TX_RX_ENGINE_ENABLE);
/* Result */
printf("errors: %d\n", errors);
}
/* Test SPI TX/RX levels */
void test_spi_tx_rx_levels(void) {
volatile unsigned int *spi_tx_32 = (unsigned int *)SPI_TX_BASE;
volatile unsigned int *spi_rx_32 = (unsigned int *)SPI_RX_BASE;
int i;
int errors = 0;
int pattern;
printf("Test SPI TX/RX levels...\n");
/* Configure Slots */
spi_mmap_ctrl_slot_control0_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_0 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
128 * SPI_SLOT_DIVIDER
);
/* Enable SPI Engine */
spi_mmap_tx_rx_engine_control_write(1 * SPI_TX_RX_ENGINE_ENABLE);
/* TX 32-bit transfers */
pattern = 0x00000001;
for (i=0; i<16; i++){
if ((spi_mmap_ctrl_tx_status_read() >> 16) != i)
errors++;
spi_tx_32[0] = pattern;
}
/* Small delay */
busy_wait(1);
/* Read RX 32-bit tranfers */
for (i=0; i<16; i++){
pattern = spi_rx_32[0];
if ((spi_mmap_ctrl_rx_status_read() >> 16) != (16-1-i))
errors++;
}
if ((spi_mmap_ctrl_tx_status_read() >> 16) != 0)
errors++;
if ((spi_mmap_ctrl_rx_status_read() >> 16) != 0)
errors++;
/* Disable SPI Engine */
spi_mmap_tx_rx_engine_control_write(0 * SPI_TX_RX_ENGINE_ENABLE);
/* Result */
printf("errors: %d\n", errors);
}
/* Test SPI TX/RX IRQs */
void test_spi_tx_rx_irqs(void) {
volatile unsigned int *spi_tx_32 = (unsigned int *)SPI_TX_BASE;
volatile unsigned int *spi_rx_32 = (unsigned int *)SPI_RX_BASE;
int errors = 0;
int data __attribute__((unused));
printf("Test SPI TX/RX IRQs...\n");
/* Configure Slots */
spi_mmap_ctrl_slot_control0_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_0 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
128 * SPI_SLOT_DIVIDER
);
/* Enable TX/RX EventManager */
spi_mmap_ev_enable_write(0);
spi_mmap_ev_pending_write(spi_mmap_ev_pending_read());
spi_mmap_ev_enable_write(SPI_SLOT_EV_TX | SPI_SLOT_EV_RX);
/* Enable SPI Engine */
spi_mmap_tx_rx_engine_control_write(1 * SPI_TX_RX_ENGINE_ENABLE);
/* TX 32-bit transfers */
spi_tx_32[0] = 0x00000001;
/* Small delay */
busy_wait(1);
/* Verify TX/RX events */
if (spi_mmap_ev_pending_read() != (SPI_SLOT_EV_TX | SPI_SLOT_EV_RX))
errors++;
/* Read RX 32-bit tranfers */
data = spi_rx_32[0];
/* Clear events */
spi_mmap_ev_pending_write(spi_mmap_ev_pending_read());
/* Verify TX/RX events */
if (spi_mmap_ev_pending_read() != 0)
errors++;
/* Disable SPI Engine */
spi_mmap_tx_rx_engine_control_write(0 * SPI_TX_RX_ENGINE_ENABLE);
/* Result */
printf("errors: %d\n", errors);
}
/* Test SPI Back-to-Back */
void test_spi_back_to_back(void) {
volatile unsigned int *spi_tx_32 = (unsigned int *)SPI_TX_BASE;
volatile unsigned int *spi_rx_32 = (unsigned int *)SPI_RX_BASE;
int errors = 0;
printf("Test SPI Back-to-Back...\n");
/* Configure Slots */
spi_mmap_ctrl_slot_control0_write(
1 * SPI_SLOT_ENABLE |
SPI_SLOT_MODE_0 * SPI_SLOT_MODE |
SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH |
SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
1 * SPI_SLOT_LOOPBACK |
8 * SPI_SLOT_DIVIDER
);
/* Enable SPI Engine */
spi_mmap_tx_rx_engine_control_write(1 * SPI_TX_RX_ENGINE_ENABLE);
/* TX 32-bit transfers */
spi_tx_32[0] = 0x00000001;
spi_tx_32[0] = 0x00000002;
/* Small delay */
busy_wait(1);
/* Read RX 32-bit tranfers */
if (spi_rx_32[0] != 0x00000001)
errors++;
if (spi_rx_32[0] != 0x00000002)
errors++;
/* Disable SPI Engine */
spi_mmap_tx_rx_engine_control_write(0 * SPI_TX_RX_ENGINE_ENABLE);
/* Result */
printf("errors: %d\n", errors);
}
2023-08-04 17:44:54 +02:00
036193d046
CHANGES: Update.
2023-08-04 16:08:00 +02:00
587981a6b8
interconnect/csr_bus: Improve description.
2023-08-01 17:11:13 +02:00
bfd4dcdefc
interconnect/ahb: Cleanup and document a bit.
2023-08-01 16:52:20 +02:00
87e2456274
CHANGES.md: Update.
2023-07-31 18:00:43 +02:00
cb06949604
soc/add_etherbone: Expose arp_entries parameter.
2023-07-31 17:59:38 +02:00
e257ff916f
soc/cores/interconnect: Rely on WaitTimer's new automatic cast to int.
2023-07-31 11:32:48 +02:00
bf79c9032a
gen/genlib/misc/WaitTimer: Cast t to int and minor cosmetic cleanup.
2023-07-31 11:27:47 +02:00
b8dc1b7757
Merge pull request #1738 from trabucayre/fix_toolchain
...
litex_setup: fix software build when liteeth or/and litesata is set (riscv toolchain issue)
2023-07-31 08:57:52 +02:00
1a74854e55
litex_setup: fix software build when liteeth or/and litesata is set (riscv toolchain issue)
2023-07-30 15:37:51 +02:00
b2e4b22145
soc/add_pcie: Add with_ptm parameter and update CHANGES.
2023-07-30 15:12:01 +02:00
91e1e53662
soc/interconnect/stream: BufferizeEndpoints params
...
BufferizeEndpoints params now includes parameters which to pipeline
the valid/data or ready path
2023-07-30 00:24:26 +02:00
ff67781f11
interconnect/axi/axi_common: Document constants.
2023-07-28 09:26:53 +02:00
ff18374c52
interconnect/axi/axi_common: Document helper functions.
2023-07-28 09:15:52 +02:00
717fb131fd
interconnect/axi: Switch to LiteXModule.
2023-07-28 09:15:22 +02:00
ed12f8787d
litex/gen: Add some comments.
2023-07-27 16:18:30 +02:00
095cfb7811
litex/gen: Split common in common/context/reduce/signal.
2023-07-27 15:02:37 +02:00
74401d6f03
CHANGES: Update.
2023-07-27 13:58:45 +02:00
bbf944c3ba
build/efinix/efinity: Fix build with 2023.1.
2023-07-27 13:55:27 +02:00
924da55ea0
stream/AsyncFIFO: Add a minimum of 2 buffers on Efinix FPGAs to fix issues on hardware.
...
Root cause still need to be understand, but when testing with another AsyncFIFO (from verilog axis),
the behavior was similar. So is it an Efinity issue? Constraint issue?
2023-07-27 13:29:05 +02:00
72a1592bee
litex/gen: Add initial/minimal LiteXContext to easily get build context from modules.
...
Still a PoC and need to think a bit more about it, but will allow fixing AsyncFIFO issue
on Efinix FPGAs.
2023-07-27 13:27:15 +02:00
20ce982da2
software/bios: Fix missing CSR_SDCARD_CORE_BASE update.
2023-07-26 16:30:52 +02:00
66b44ecd60
soc/add_uart: Fix stub behavior (sink/source swap), thanks @zyp.
2023-07-26 12:26:16 +02:00
0f1fdea893
build/xilinx/vivado: Also generate design checkpoint after synthesis and placement.
...
This help exploring/constraining complex designs by using Vivado GUI and design checkpoint.
2023-07-21 19:53:28 +02:00
35cd744adc
CHANGES: Update.
2023-07-21 15:16:42 +02:00
330d61d2bd
soc/add_pcie: Remove MSI workaround on Ultrascale(+) now that root cause is understood/fixed (thanks @smunaut).
2023-07-21 14:50:38 +02:00
aae15737cd
CHANGES: Update.
2023-07-20 16:30:48 +02:00
c00f61d9d7
tools: Update to new sdcard core name.
2023-07-20 16:29:05 +02:00
6693a723d1
software: Update to new sdcard core name.
2023-07-20 16:28:51 +02:00
0152e7de8e
soc/add_sata: Use name parameter to allow multiple sdcard instances.
2023-07-20 16:28:22 +02:00
e364316814
soc/add_sata: Use name parameter to allow multiple sata instances.
2023-07-20 16:02:03 +02:00
f995d74e55
soc/add_uartbone: Rename name parameter to uart_name to allow multiple uartbone (also for consistency with other cores) and other minor cleanups.
2023-07-20 15:42:03 +02:00
6e78db6767
soc/add_bus_master: Use name where possible to avoid automatic naming and improve log readability.
2023-07-20 15:15:44 +02:00
f6da67fb38
soc/add_pcie: Add optional data_width parameter.
2023-07-20 10:35:10 +02:00
69c6fa11d2
build/lattice/common/lattice_ecp5_trellis_special_overrides: Add missing DifferentialOutput.
2023-07-17 17:08:35 +02:00
6ab156e225
soc/cores: Fix regressions.
2023-07-17 11:48:39 +02:00
79a82dc732
tools/litex_json2dts_linux: Remove duplicated clock definition.
...
Keep clock definition introduced by 9b67898e99
2023-07-17 11:27:07 +02:00
3d101b9749
integration/export: When csr_base is specified, make CSR regions definition relative to it.
...
Useful for PCIe based systems when internal CSR base is automatically added by the logic.
2023-07-17 11:14:33 +02:00
3fc16f54f1
soc/cores/cpu: Switch to LiteXModule.
2023-07-17 09:26:58 +02:00
39ff69ade7
cores/spi: Switch to LiteXModule.
2023-07-17 09:14:47 +02:00
028f7eb72f
cores/ram: Switch to LiteXModule.
2023-07-17 09:12:25 +02:00
b35c6580e8
soc/cores/clock: Switch to LiteXModule.
2023-07-15 21:54:07 +02:00
8103cf7851
soc/cores: Switch cores to LiteXModule (still need to do cpu, ram, clk, spi).
2023-07-14 22:19:14 +02:00
6e46710678
gen/fhdl/module: Fix CSR clock domain renaming to cores converted to LiteXModule, thanks @smunaut.
2023-07-14 10:01:32 +02:00
987a35e1ec
Merge pull request #1729 from riktw/master
...
Currently using a lite or minimal Vexriscv config with debug and brea…
2023-07-13 15:21:51 +02:00
3a2586c48b
soc/add_pcie: Remove csr_ordering parameter (not useful and remove on litepcie).
2023-07-12 19:42:54 +02:00
f9e32eb3eb
CHANGES: Update.
2023-07-11 16:42:21 +02:00
Gwenhael Goavec-Merou
Icenowy Zheng
Florent Kermarrec
rowanG077
Dolu1990