Sebastien Bourdeauducq
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a148af97ba
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soc: retrieve csr and memory regions using methods
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2015-04-01 16:49:32 +08:00 |
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Sebastien Bourdeauducq
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8b19a11cd7
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soc: use add_wb_master function
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2015-04-01 15:56:54 +08:00 |
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Sebastien Bourdeauducq
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2a1112b912
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soc: simplify/fix csr busword
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2015-04-01 15:48:56 +08:00 |
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Sebastien Bourdeauducq
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04f29e97e2
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soc: remove unnecessary imports
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2015-04-01 15:15:09 +08:00 |
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Sebastien Bourdeauducq
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5113301130
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soc: improve memory region conflict check
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2015-04-01 15:14:02 +08:00 |
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Sebastien Bourdeauducq
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980791e2b8
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soc: remove ns function
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2015-04-01 14:33:12 +08:00 |
Florent Kermarrec
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b313772a0c
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sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0)
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2015-03-29 12:34:40 +02:00 |
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Florent Kermarrec
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be20fbabe4
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soc: limit main_ram_size to 256MB (we should modify mem_map to allow larger memories, this was the probably ARTIQ runtime issue....!!)
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2015-03-28 23:35:44 +01:00 |
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Florent Kermarrec
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0649ded5fd
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soc: simplify main_ram_size computation and share it between LASMIcon and Minicon
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2015-03-28 23:10:33 +01:00 |
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Florent Kermarrec
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ba8b24df57
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sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy
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2015-03-25 16:57:38 +01:00 |
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Florent Kermarrec
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7ea9e2ba89
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sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings.
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2015-03-25 16:56:29 +01:00 |
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Florent Kermarrec
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30c2521eb0
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sdram: pass sdram_controller_settings to SDRAMSoC
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2015-03-21 23:12:18 +01:00 |
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Florent Kermarrec
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70469e1f37
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sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit)
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2015-03-21 21:32:39 +01:00 |
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Florent Kermarrec
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9bc71f374a
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rename sdram mapping to main_ram
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2015-03-21 21:01:46 +01:00 |
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Florent Kermarrec
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c55199deb9
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misoclib/soc: add _integrated_ to cpu options to avoid confusion
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2015-03-21 20:51:37 +01:00 |
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Florent Kermarrec
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6e4b7c6cfd
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sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
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2015-03-21 12:55:39 +01:00 |
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Florent Kermarrec
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82fe83a1c4
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sdram: raise NotImplementedError if Minicon is used others memories than SDR (not functional for now)
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2015-03-19 16:08:03 +01:00 |
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Florent Kermarrec
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28d04ec300
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soc: rename with_sdram option to with_main_ram (with_sdram was confusing)
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2015-03-14 00:49:19 +01:00 |
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Sebastien Bourdeauducq
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32676fffd2
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soc/sdram: sync with new mibuild toolchain management
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2015-03-13 23:19:08 +01:00 |
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Florent Kermarrec
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cd6c04b24f
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soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx in november 2014, remove it when fixed by Xilinx
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2015-03-12 17:12:56 +01:00 |
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Florent Kermarrec
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1b58813d13
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soc: do_exit is now provided by modules
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2015-03-09 17:18:42 +01:00 |
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Florent Kermarrec
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af66ca7bad
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uart: add phy autodetect function
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2015-03-06 10:19:29 +01:00 |
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Florent Kermarrec
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bee8ccf6c7
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soc: enforce cpu_reset_address to 0 when with_rom is True
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2015-03-06 08:21:16 +01:00 |
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Florent Kermarrec
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2b9397ff5b
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targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)
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2015-03-06 07:56:45 +01:00 |
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Florent Kermarrec
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0bcd6daf63
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soc: remove is_sim function
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2015-03-03 10:15:11 +01:00 |
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Florent Kermarrec
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905be50451
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sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy
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2015-03-03 09:55:25 +01:00 |
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Florent Kermarrec
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9df60bf98e
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lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True)
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2015-03-03 09:02:53 +01:00 |
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Florent Kermarrec
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473997df26
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cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
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2015-03-02 16:52:17 +01:00 |
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Florent Kermarrec
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8280acd3a7
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sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core
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2015-03-02 12:17:49 +01:00 |
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Florent Kermarrec
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3465db25a7
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soc/sdram: be more generic in naming
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2015-03-02 11:55:28 +01:00 |
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Florent Kermarrec
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97331153e0
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sdram: create core dir and move lasmicon/minicon in it
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2015-03-02 11:38:22 +01:00 |
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Florent Kermarrec
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de698c51e4
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sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner)
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2015-03-02 11:29:43 +01:00 |
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Florent Kermarrec
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c0b38e4905
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sdram/lasmicon: create a separate file for the crossbar and remove it from lasmibus
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2015-03-02 09:18:32 +01:00 |
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Florent Kermarrec
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7300879b7f
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sdram: move dfii to phy
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2015-03-02 09:08:28 +01:00 |
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Florent Kermarrec
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b305b7828a
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sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it
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2015-03-02 08:36:39 +01:00 |
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Florent Kermarrec
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f58394f6af
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soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
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2015-03-01 18:25:47 +01:00 |
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Florent Kermarrec
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bd4d3cd73b
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uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
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2015-03-01 12:14:34 +01:00 |
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Florent Kermarrec
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144ee7ea9f
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soc: fix register_rom
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2015-02-28 23:51:51 +01:00 |
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Florent Kermarrec
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5c43d4d091
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litescope: create example design derived from SoC that can be used on all targets
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2015-02-28 22:19:24 +01:00 |
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Florent Kermarrec
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165a5b6760
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soc: use self.cpu_reset_address as rom mem_map address and increase default bios size to 0xa000
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2015-02-28 20:04:51 +01:00 |
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Florent Kermarrec
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6107b7844a
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test implementation on all targets and fix issues
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2015-02-28 12:04:51 +01:00 |
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Florent Kermarrec
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8564b7eb6a
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soc: move SDRAMSoC to a separate sdram.py file (ideally part of SDRAMSoC should move mem/sdram)
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2015-02-28 11:44:14 +01:00 |
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Florent Kermarrec
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69e869893d
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remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
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2015-02-28 11:36:15 +01:00 |