a7378a721c
.gitmodules: use our copy of tapcfg since https://github.com/nizox/tapcfg no longer exists.
2018-12-23 19:47:48 +01:00
2deffd8c8a
build/sim/verilator: compile sim just before running and not when building.
2018-12-21 09:59:34 +01:00
291843ee76
Merge pull request #144 from mithro/nextpnr-migen-update
...
Integrate latest migen changes for lattice/icestorm.
2018-12-20 11:35:42 -08:00
53731b792b
Integrate latest migen changes for lattice/icestorm.
...
Integrated up to 37db6bb52532b6d1c6bc8b724c2e8c6a38546c2a.
2018-12-20 11:33:19 -08:00
180912a7a3
build/sim: handle verilog $finish and if coverage is enabled, write report at the end of the simulation.
2018-12-20 10:38:40 +01:00
b6c98cab0d
platforms/kcu105: change internal vref to 0.84v (recommended value for ddr4)
2018-12-19 11:33:32 +01:00
ebe0d567f8
bios/sdram: only show read delays when they are valid.
2018-12-19 11:19:47 +01:00
67a2590235
bios/sdram: reduce write leveling scan range
2018-12-19 11:18:19 +01:00
fe5cef4294
soc/cores/clock: remove return on S7PLL.create_clkout
2018-12-19 09:14:26 +01:00
eda1a83ea9
platforms/kcu105: set internal vref on ddr4 banks
2018-12-18 21:38:23 +01:00
a27b5a3be1
update Ultrascale DDRPHY
2018-12-18 11:25:21 +01:00
1c1c1bd122
Merge pull request #141 from mithro/xst-fix
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Fix `-vlgincdir` for xst.
2018-12-17 21:24:15 -08:00
8b2abc7e89
Fix `-vlgincdir` for xst.
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The command line is of the form;
```
-vlgincdir {"path1" "path2"}
```
Fixes the following error;
```
WARNING:Xst:3164 - Option "-vlgincdir" found multiple times in the command line. Only the first occurence is considered.
```
2018-12-17 21:11:14 -08:00
f8f3683aaa
bios/sdram: reduce scans verbosity on ultrascale
2018-12-17 16:00:44 +01:00
efce434aa9
bios/sdram: use ddrphy_half_sys8x_taps_read() for KUSDDRPHY
2018-12-17 11:43:21 +01:00
0ade06c0f0
Merge pull request #138 from mithro/mainram-hack
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Hack to fix #136 .
2018-12-16 14:42:36 -08:00
22d454efcd
Hack to fix #136 .
2018-12-16 14:40:10 -08:00
fa6fef1e15
Merge pull request #135 from mithro/icestorm-ice40up5k
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Add uwg30 package and up3k part.
2018-12-16 14:04:19 -08:00
9481781d1c
Add uwg30 package and up3k part.
2018-12-16 14:03:29 -08:00
e9f1049200
soc/cores/cpu/vexriscv: add add_debug method for debug variants
2018-12-12 10:01:49 +01:00
35155e5172
soc/cores/cpu/vexriscv: add support for the new variants.
2018-12-12 09:39:30 +01:00
2ace45e6f8
soc/cores/cpu/vexriscv: update submodule
2018-12-12 09:38:53 +01:00
6d6c2b4c45
soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v)
2018-12-12 09:38:10 +01:00
584fd51c01
build/sim/verilator: add support for plaform.sources, some cleanup
2018-12-12 09:37:24 +01:00
c9915f89ce
build/microsemi/libero_soc: fix typos
2018-12-12 09:34:43 +01:00
99578bc68c
gen/sim/core: add args support on Display
2018-12-09 09:46:10 +01:00
fa260f5b42
gen/fhdl: add simulation Display, Finish support.
...
In some simulation cases, it's easier to add debug traces directly in the code
than in the verilog/Migen testbench. This adds support for verilog $display in
Migen code.
Being able to terminate a simulation from the code is also useful, this also
add support for verilog $finish.
2018-12-09 09:45:17 +01:00
92a6169d2a
build/sim: add coverage parameter to enable code coverage
2018-12-09 08:10:50 +01:00
0c687bc29e
soc/interconnect/stream: add support for buffered async fifo
2018-12-08 01:24:08 +01:00
bf3b4eec34
gen: integrate migen changes
2018-12-04 21:06:51 +01:00
96527b5a3a
soc/interconnect/stream/gearbox: remove bit reversing by changing words order
2018-11-30 23:12:30 +01:00
1c8c2426b9
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-11-27 17:45:07 +01:00
8887fc24c4
build/xilinx/vivado: disable xpm by default (can be enabled by passing enable_xpm=True to build).
...
Old version of Vivado don't have XPM support and enable it break the build.
Enabling XPM is only useful in some cases, we can do it manually.
2018-11-27 17:42:39 +01:00
cc4ba65659
Merge pull request #130 from jfng/master
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litex_sim: add --trace argument
2018-11-27 17:35:03 +01:00
ec46beeb47
targets/ulx3s, versa_ecp5: use ECP5PLL
2018-11-27 17:31:53 +01:00
71398e0155
litex_sim: add --trace argument
2018-11-27 17:26:32 +01:00
18048eb454
cores/clock: test and fix ECP5PLL, phase still not implemented.
2018-11-27 17:24:22 +01:00
20dd95c541
boards/platforms/ulx3s: add gpios 0-3
2018-11-27 14:15:35 +01:00
909cff1940
bios/sdram: flush l2 cache only when present
2018-11-26 18:37:45 +01:00
2ad83778bf
bios: allow testing main_ram at init when using an external controller
2018-11-26 15:21:00 +01:00
cdfe0454bb
build/microsemi/libero_soc: small cleanup
2018-11-26 11:35:06 +01:00
4592e3235b
Merge pull request #128 from mithro/small-fix
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Two small fixes
2018-11-26 09:48:10 +01:00
4f565c5179
stream.Endpoint: Pass extra arguments to superclass.
2018-11-25 12:57:11 -08:00
3b9e4c4df6
wishbone.SRAM: Support non-32bit wishbone widths.
2018-11-25 12:56:37 -08:00
515c06219a
cores/clock: add ECP5PLL
2018-11-24 00:47:38 +01:00
7623b5dd96
soc/interconnect/stream/gearbox: inverse bit order
2018-11-23 18:34:24 +01:00
d32e393033
soc/cores/spi_flash: add missing endianness parameter
2018-11-23 18:33:53 +01:00
c954943e02
platforms/avalanche: add IOStandard on ddram pins
2018-11-23 12:47:45 +01:00
09a1cda943
build/microsemi/libero_soc: associate timings constraints with synthesis/place&route/timing verification
2018-11-23 09:30:13 +01:00
a98e1ad689
build/microsemi/libero_soc: add additional_timing_constraints
2018-11-23 09:04:42 +01:00
Florent Kermarrec
Tim Ansell
Jean-François Nguyen