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Author SHA1 Message Date
Florent Kermarrec
0d2db23603 litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink) 2015-05-25 13:55:15 +02:00
Florent Kermarrec
cb053dc011 liteusb/core/packet: fix missing , 2015-05-25 13:53:02 +02:00
Florent Kermarrec
1bb5a05488 litesata: add striping module for use of multiple HDDs. 2015-05-23 14:12:20 +02:00
Florent Kermarrec
5daba9af68 litesata: do some cleanup and prepare for RAID 2015-05-23 14:08:56 +02:00
Florent Kermarrec
a5f495aeac fhdl/verilog: add reserved keywords 2015-05-23 14:01:08 +02:00
Florent Kermarrec
9cabcf14e9 migen/genlib/record: add leave_out parameter to connect 
Modules doing dataflow adaptation often need to connect most of the signals between endpoints except the one concerned by the adaptation.
This new parameter ease that by avoid manual connection of all signals.
 2015-05-23 13:59:09 +02:00
Guy Hutchison
5390540d3c example of instance usage 2015-05-20 01:14:42 +08:00
Florent Kermarrec
ada131dbe0 vpi: avoid some code duplication between windows and linux 2015-05-13 10:48:08 +02:00
Florent Kermarrec
f6624b34f0 migen/actorlib/spi: apply missing CSR renaming 2015-05-13 10:17:31 +02:00
Florent Kermarrec
76302d7aa6 vpi: cleanup (thanks sb) 2015-05-13 10:13:14 +02:00
Florent Kermarrec
98cf103c65 vpi: fix and simplify windows simulation (ends of msg were ignored) 2015-05-13 03:03:34 +02:00
Florent Kermarrec
b0f159421c Merge branch 'master' of https://github.com/m-labs/migen 2015-05-12 16:16:24 +02:00
Florent Kermarrec
88a406ebec migen/genlib/misc: replace Timeout with WaitTimer from artiq 2015-05-12 16:14:58 +02:00
Florent Kermarrec
d9b15e6ef6 cores: replace Timeout with new WaitTimer 2015-05-12 16:14:38 +02:00
Yann Sionneau
9194fe43a1 travis: install conda dependencies after activating the virtual env 2015-05-12 14:06:16 +02:00
Yann Sionneau
c1088f4666 travis: get-anaconda.sh does not take args anymore 2015-05-12 13:58:08 +02:00
Florent Kermarrec
a99aa9c7fd uart: rename wishbone to bridge 2015-05-09 16:24:28 +02:00
Florent Kermarrec
fb5397aa82 uart: remove litescope dependency for UARTWishboneBridge and remove frontend 2015-05-09 16:08:20 +02:00
William D. Jones
fe6eef7069 Windows simulation support 2015-05-09 21:09:52 +08:00
Florent Kermarrec
1fd189512f liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core) 2015-05-08 23:10:08 +02:00
Robert Jordens
99fb0d4619 ise: move -user_new_parser to xst_opt 2015-05-08 11:18:45 +08:00
Florent Kermarrec
4d902b578c liteusb/phy/ft245: rename "ftdi" clock domain to "usb" 2015-05-07 20:03:12 +02:00
Florent Kermarrec
d9111f6a04 litesata: fix packets figure in frontend doc 2015-05-07 11:06:05 +02:00
Sebastien Bourdeauducq
566d973049 README: add note about submodules 2015-05-07 16:29:30 +08:00
Florent Kermarrec
5516a49696 litesata: add doc for frontend 2015-05-06 03:57:07 +02:00
Florent Kermarrec
6908ddbaf9 litesata: cleanup README/doc 2015-05-06 02:02:22 +02:00
Florent Kermarrec
7bdcbc94cd litesata: use (some) settings from vivado 2015.1, try to follow all ug476 recommendations to initialize GTX (...), remove automatic reset on top. 
Works fine @ 3Gbps, still not working @6.0Gbps
 2015-05-06 01:33:02 +02:00
Sebastien Bourdeauducq
5d5d5edfe2 spiflash: fix miso bitbang with large DQ 2015-05-06 00:05:25 +08:00
Florent Kermarrec
553262bcc1 soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment... 2015-05-04 12:28:49 +02:00
Florent Kermarrec
438a0856c5 misoclib/cpu: merge git.py in identifier 2015-05-02 18:42:33 +02:00
Florent Kermarrec
da711ad5f1 liteusb: add simple example design with wishbone bridge and software to control it 2015-05-02 18:21:18 +02:00
Florent Kermarrec
c98bd9fd79 rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq) 2015-05-02 17:07:58 +02:00
Florent Kermarrec
145398d874 liteeth/core/mac: minor cleanup 2015-05-02 16:48:57 +02:00
Florent Kermarrec
e9ef11620f liteusb/frontend/wishbone: use new packetized mode (allow grouping response in a single packet) 2015-05-02 16:22:45 +02:00
Florent Kermarrec
1761bfba8a litescope/frontend/wishbone: add support for packetized mode 2015-05-02 16:22:43 +02:00
Florent Kermarrec
ff51bde7f0 liteusb/software/wishbone: optimize writes/reads (send a single packet for a command) 2015-05-02 16:22:40 +02:00
Florent Kermarrec
e8c01ff4aa do more test with last changes fix small issues 2015-05-02 16:22:38 +02:00
Florent Kermarrec
63b8797978 liteeth: move mac to core 2015-05-02 16:22:35 +02:00
Florent Kermarrec
a4617014f4 cores: avoid having too much directories when possible (for simple cores or cores contained in a single file) 2015-05-02 16:22:33 +02:00
Florent Kermarrec
3ebe877fd2 use similar names for wishbone bridges and move wishbone drivers to [core]/software 2015-05-02 16:22:30 +02:00
Zach Smith
1832f27220 targets/pipistrello: add flash sizes 2015-05-02 09:59:24 +08:00
Florent Kermarrec
5e649a6577 litescope: add basic LiteScopeUSB2WishboneFTDIDriver (working but need to be optimized) 2015-05-01 20:45:04 +02:00
Florent Kermarrec
c03c41eb77 litescope: rename host directory to software (to be coherent with others cores) 2015-05-01 20:45:02 +02:00
Florent Kermarrec
a8b8af220a liteusb: add basic wishbone frontend (We could also reuse Etherbone in the future) 2015-05-01 20:44:59 +02:00
Florent Kermarrec
cd3a51ada6 litescope: fix missing source ack on LiteScopeWishboneBridge 2015-05-01 20:44:57 +02:00
Florent Kermarrec
1281a463d6 litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data). 
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
 2015-05-01 17:51:18 +02:00
Florent Kermarrec
23126415d3 litescope: use full name in io.py 2015-05-01 17:49:31 +02:00
Florent Kermarrec
23ba1ccb52 targets/minispartan6: add USBSoC (working, should also be usable on pipistrello) 2015-05-01 16:22:45 +02:00
Florent Kermarrec
da0fe2ecfb liteusb: refactor software (use python instead of libftdicom in C) and provide simple example. 
small modifications to fastftdi.c are also done to select our interface (A or B) and mode (synchronous, asynchronous)
 2015-05-01 16:22:26 +02:00
Florent Kermarrec
603b4cdc8c liteusb: continue refactoring (virtual UART and DMA working on minispartan6) 
- rename ft2232h phy to ft245.
- make crc optional
- fix depacketizer
- refactor uart (it's now only a wrapper around standard UART)
- fix and update dma
 2015-05-01 16:11:15 +02:00