ea9c1b8e69
fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code"
...
This probably breaks simulation with Icarus Verilog (and others simulators?)
2015-03-18 14:59:22 +01:00
2fc2f8a6c0
migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb)
2015-03-18 14:41:43 +01:00
bdc47b205a
Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)"
...
This breaks simulations, and we will try to use the "reg name = value" syntax instead.
This reverts commit e946f6e453
2015-03-18 12:08:25 +01:00
cb4be52922
targets: add Lattice ECP3 versa
2015-03-17 19:09:43 +01:00
89fefef3f8
genlib/io: add optional external rst to CRG
2015-03-17 16:22:22 +01:00
70f1f96fda
litescope/drivers: do not build regs when addrmap is None
2015-03-17 16:04:31 +01:00
a266deb58e
LiteXXX cores: fix frequency print in test/test_regs.py
2015-03-17 16:01:25 +01:00
d2cb41bc63
LiteXXX cores: convert port parameter to int if is digit in test/make.py
2015-03-17 15:58:21 +01:00
500e58ce7d
mibuild/platform/versa: fix clock_constraints
2015-03-17 15:25:10 +01:00
e07b7f632c
mibuild/lattice: use ODDRXD1 and new synthesis directive
2015-03-17 14:59:36 +01:00
b7d7fe1a4c
fhdl/special: add optional synthesis directive (needed by Synplify Pro)
2015-03-17 14:59:05 +01:00
022ac26c22
mibuild/lattice: add LatticeAsyncResetSynchronizer
2015-03-17 12:42:36 +01:00
2327710387
liteeth/phy/gmii : set tx_er to 0 only if it exits
2015-03-17 12:24:06 +01:00
408d0fd2dd
liteeth: use default programmer in make.py
2015-03-17 12:12:21 +01:00
ec6ae75065
liteeth: use CRG from Migen in base example
2015-03-17 12:11:51 +01:00
c06ab82f13
mibuild/platforms/versa: add ethernet clock constraints
2015-03-17 12:04:00 +01:00
a874f85854
litescope: use CRG from Migen
2015-03-17 11:52:54 +01:00
ba2aeb08be
mibuild/platforms/versa: add rst_n
2015-03-17 11:51:34 +01:00
6dd8d89c6c
mibuild/lattice: fix LatticeDDROutput
2015-03-17 09:40:25 +01:00
b2f32ad124
targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains)
2015-03-17 01:07:44 +01:00
9adf3f02f2
fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code
...
it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
2015-03-17 00:40:26 +01:00
e946f6e453
fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)
2015-03-16 23:47:07 +01:00
faf185d58d
liteeth: make gmii phy generic
2015-03-16 23:04:37 +01:00
b5a9909b08
mibuild/xilinx/common: add LatticeDDROutput
2015-03-16 22:57:18 +01:00
993059a59c
mibuild/xilinx/common: add XilinxDDROutput
2015-03-16 22:53:05 +01:00
69ce6dd48c
migen/genlib/io: add DDRInput and DDROutput
2015-03-16 22:47:13 +01:00
b3b1209c62
mibuild/platforms: add ethernet to versa
2015-03-16 22:24:10 +01:00
fab0b0b161
mibuild/platforms: add user_dip_btn to versa
2015-03-16 22:11:15 +01:00
d6041879dd
mibuild/lattice: use new Toolchain/Platform architecture
2015-03-16 21:24:21 +01:00
e903b62af1
mibuild/altera: use new Toolchain/Platform architecture
2015-03-16 21:07:55 +01:00
f7bfa13144
mibuild: add initial Lattice Diamond support (with ECP3 Versa board platform skeleton)
2015-03-16 19:02:34 +01:00
beeaefccea
move pytholite to separate repos
2015-03-14 22:48:03 +01:00
c824379878
fhdl/visit: fix TransformModule
2015-03-14 17:45:11 +01:00
aef9275c99
mibuild/xilinx: export special_overrides dictionary
2015-03-14 10:45:11 +01:00
d8b59c03a2
litesata: avoid hack on kc705 platform with new mibuild toolchain management
2015-03-14 01:08:36 +01:00
28d04ec300
soc: rename with_sdram option to with_main_ram (with_sdram was confusing)
2015-03-14 00:49:19 +01:00
d34b7d7a6b
mibuild/xilinx: remove obsolete CRG_DS
2015-03-14 00:27:24 +01:00
d09529d483
targets/simple: use mibuild default clock
2015-03-14 00:11:59 +01:00
6a979a8023
mibuild: sanitize default clock management
2015-03-14 00:10:08 +01:00
702d177c85
mibuild: get rid of Platform factory function, cleanup
2015-03-13 23:25:15 +01:00
32676fffd2
soc/sdram: sync with new mibuild toolchain management
2015-03-13 23:19:08 +01:00
c3c7f627d9
liteeth/phy: typo (thanks sb)
2015-03-12 21:54:10 +01:00
ff266bc2ee
migen/genlib/io: add DifferentialOutput and Xilinx implementation
2015-03-12 19:30:57 +01:00
bf28664cb4
genlib/io.py: fix copy/paste error (thanks rjo)
2015-03-12 18:49:49 +01:00
c8ba8cde8e
migen/genlib: add io.py to define generic I/O specials to be lowered by mibuild
2015-03-12 18:38:53 +01:00
1b72b81f9c
targets/simple: use new generic DifferentialInput
2015-03-12 18:36:04 +01:00
f18ae9b9fe
targets/simple: insert IBUFDS for Xilinx devices (not implemented for others vendors)
2015-03-12 17:25:01 +01:00
cd6c04b24f
soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx in november 2014, remove it when fixed by Xilinx
2015-03-12 17:12:56 +01:00
767d45727a
uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty).
2015-03-12 16:57:38 +01:00
00e8616de2
mibuild/sim: clean up (thanks sb)
2015-03-10 16:41:52 +01:00
Florent Kermarrec
Sebastien Bourdeauducq