b192103822
cores/hyperbus: Fix bytes order on register writes.
2024-04-12 16:06:26 +02:00
fb519ac260
test/test_hyperbus: Add test_hyperram_reg_write.
2024-04-12 15:21:57 +02:00
a32db7abad
cores/hyperbus: Add with_csr parameter to make Register interface optional.
2024-04-12 15:21:32 +02:00
441d05ee36
core/hyperbus: Start testing Register writes.
2024-04-11 18:39:48 +02:00
59756b4342
cores/hyperbus: Test and fix HyperRAM register read accesses.
...
Seems OK:
Identification Register 0 : 00000e76
Identification Register 1 : 00000009
Configuration Register 0 : 00008f2f
Configuration Register 1 : 0000ffc1
reg_control: 302
reg_status: 2
reg_debug: 8
2024-04-11 18:29:48 +02:00
2384d6fbd4
cores/hyperbus: Add initial HyperRAM Register access over CSRs.
...
Will be used to get HyperRAM characteristics and also to configure latency and enable varialble latency.
Untested yet.
2024-04-11 17:51:47 +02:00
b8ca87ece5
build/openocd: disabled 'poll off' because not supported by ECP5
2024-04-11 15:13:52 +02:00
3864615f6f
tools/litex_json2dts_linux.py: improved cpu_isa_extension attribute (fdc) and fixed kernel panic during rocket booting with linux
2024-04-06 08:13:56 +02:00
06009c57a3
build/xilinx/common: Fix missing clk parameter on XilinxSDRTristateImpl.
2024-04-05 16:04:29 +02:00
dc78c3f47b
soc/interconnect/stream/ClockDomainCrossing: Add a Buffer when same Clk Domains when buffered=True.
2024-04-04 13:02:17 +02:00
a36fbc86ea
Merge pull request #1911 from davidar/sim-vsync
...
sim/video: Add option to render only on frame vsync
2024-04-02 10:54:05 +02:00
7ad444b2a9
Merge pull request #1912 from motec-research/efinity_fix_pin_name
...
build/efinix/platform: fix get_pin_name()
2024-04-02 10:48:19 +02:00
38a8a171dd
integration/builder: Replace soc_core's initialize_memory with optional "init_mems" method.
...
Make sure to also attach Builder to SoC to allow easily get/use builder properties in init_mems method.
2024-04-02 10:43:01 +02:00
31508ddfa4
soc: Add separators for SoC Main Components.
2024-04-02 10:25:59 +02:00
06083c7863
soc/init_ram: Define and use contents_size.
2024-04-02 10:21:35 +02:00
ca04858b39
integration/builder: Switch to SoC.init_rom directly and remove initialize_rom that is no longer used.
2024-04-02 10:16:43 +02:00
175aab73a8
soc/SoC: Add init_ram method from init_rom, allowing initilization of any RAM of the SoC and switch init_rom to it.
2024-04-02 10:09:38 +02:00
9f49b13f8c
soc_core: Minor cosmetic changes.
2024-04-02 09:15:33 +02:00
f181eabebb
soc/init_rom: Add SoCError when ROM Size < Contents Size and cosmetic cleanups.
2024-04-02 09:12:03 +02:00
0601bf51c4
Merge pull request #1856 from motec-research/soc_initialize_memory
...
soc/builder: add initialize_memory()
2024-04-02 17:30:12 +11:00
0cb101da25
build/efinix/platform: fix get_pin_name()
...
get_pin_name did not include the resource index, so additional core
instances were generated with identical pin names. See below for
examples.
Also only adds slice index for slices with more than one io for cleaner
naming.
("i2c", 0,
Subsignal("scl", Pins(...)),
Subsignal("sda", Pins(...)),
),
("i2c", 1,
Subsignal("scl", Pins(...)),
Subsignal("sda", Pins(...)),
),
Before:
output wire i2c0_oe,
input wire i2c0_scl,
input wire i2c0_sda,
input wire i2c1_scl,
input wire i2c1_sda,
input wire i2c_scl0_IN,
input wire i2c_scl0_IN_1,
input wire i2c_scl0_IN_2,
output wire i2c_scl0_OE,
output wire i2c_scl0_OE_1,
output wire i2c_scl0_OE_2,
input wire i2c_sda0_IN,
input wire i2c_sda0_IN_1,
input wire i2c_sda0_IN_2,
output wire i2c_sda0_OE,
output wire i2c_sda0_OE_1,
output wire i2c_sda0_OE_2,
After:
output wire i2c0_oe,
input wire i2c0_scl,
input wire i2c0_scl_IN,
output wire i2c0_scl_OE,
output wire i2c0_scl_OUT,
input wire i2c0_sda,
input wire i2c0_sda_IN,
output wire i2c0_sda_OE,
output wire i2c0_sda_OUT,
input wire i2c1_scl,
input wire i2c1_scl_IN,
output wire i2c1_scl_OE,
output wire i2c1_scl_OUT,
input wire i2c1_sda,
input wire i2c1_sda_IN,
output wire i2c1_sda_OE,
output wire i2c1_sda_OUT,
2024-04-02 11:52:31 +11:00
a763e82d86
soc/builder: add initialize_memory()
...
Allows the target soc to override memory initialization:
rom and/or ram.
2024-04-02 11:37:31 +11:00
5d2676482f
sim/video: Add option to render only on frame vsync
2024-03-29 11:24:16 +10:00
87137c3027
CHANGES.md: Update.
2024-03-28 14:24:12 +01:00
7b0985a6bc
Merge pull request #1909 from davidar/sim-rgba
...
sim/video: Change pixel format to RGBA
2024-03-28 14:21:24 +01:00
c73f310179
Merge pull request #1908 from Irvise/neorv32_update
...
Update NeoRV32 CPU to v1.9.7
2024-03-28 14:20:59 +01:00
60920f3c7d
integration/export: Also fix MockCSRRegion base definition.
2024-03-27 17:09:33 +01:00
e74b7f7ebe
integration/export: Fix MockCSRRegion C header export.
...
Use full address for export since when used, CSR_BASE is related to the top level SoC and not to the imported external mapping.
2024-03-27 16:49:09 +01:00
1895dd36e2
tools/litex_sim: Add --with-video-colorbars option
2024-03-26 20:23:51 +10:00
6735728340
sim/video: Change pixel format to RGBA
2024-03-26 20:22:58 +10:00
4389742a4f
CHANGES.md: Update.
2024-03-25 19:10:40 +01:00
40ff2da45c
Update NeoRV32 CPU to v1.9.7
2024-03-23 10:18:07 +01:00
9156d7902e
tools/litex_json2dts_linux: increment interrupts value by one for rocket
2024-03-21 20:54:08 +01:00
68108e396d
tools/litex_json2dts_linux: added isa-base,isa-extensions required by kernel > 6.6.0 in replacement to isa
2024-03-21 20:53:19 +01:00
29aa8f0771
Merge pull request #1906 from jdavidberger/master
...
Avoid extra timing delays for NXLRAM path
2024-03-21 09:14:39 +01:00
c640efcec3
Avoid extra timing delays for NXLRAM path
2024-03-20 14:58:08 -06:00
8f04542c15
Revert "build/openocd: Allow config file to be searched from local dirs"
...
This reverts commit a7d441488c
2024-03-20 16:44:58 +01:00
46ff7cdee5
Merge pull request #1901 from FlyGoat/zynq7000_openocd
...
Zynq7000 litex_server OpenOCD JTAG fixes
2024-03-20 16:41:22 +01:00
c2fd1e9a49
litex_json2dts_linux: Switch to cpu_name instead of cpu_human_name.
2024-03-08 18:53:44 +01:00
49f12ea297
soc/add_cpu: Add CPU_NAME constant.
2024-03-08 18:51:26 +01:00
a7d441488c
build/openocd: Allow config file to be searched from local dirs
...
To sort out path for boards using OpenOCD config file shipped with
OpenOCD itself.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-03-07 19:54:04 +00:00
94e644ba92
Merge pull request #1902 from trabucayre/rocket_update
...
Rocket update
2024-03-07 13:38:02 +01:00
68991b6a40
tools/litex_json2dts_linux: added missing rocket's nodes (align to pythondata-cpu-rocket dts)
2024-03-07 11:59:48 +01:00
54f8d90d38
soc/cores/cpu/rocket/core: align config (XCACHE, XTLB) to pythondata-cpu-rocket master
2024-03-07 09:00:32 +01:00
149080fc8b
cpu/naxriscv/core: Minor cleanups and add xlen to human_name.
2024-03-06 16:01:38 +01:00
18720e29cc
build/openocd: Fix tap name for zynq_7000
...
zynq_7000 have a special tap name fpr PL defined in openocd
config file.
Just hardcode it here.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-03-05 21:44:55 +00:00
35dd87499c
build/openocd: Disable polling after init
...
OpenOCD's event polling mechanism may interfere with
jtagstream, as we don't expect any command sent by
openocd itself.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-03-05 21:34:56 +00:00
f304cba8a6
Merge pull request #1897 from machdyne/master
...
support TQFP144 ECP5 package
2024-03-05 21:26:22 +01:00
98c15331be
Merge pull request #1899 from meiniKi/fazyrv_path
...
FazyRV: Fix minor typo in path check
2024-03-05 21:24:49 +01:00
1511c8f200
tools/litex_json2dts_linux: don't hardcode phandle for clint's interrupts-extended
2024-03-05 16:10:42 +01:00
Florent Kermarrec
Gwenhael Goavec-Merou
AndrewD
Andrew Dennison
David A Roberts
Fernando Oleo Blanco
jdavidberger
Gwenhael Goavec-Merou
Jiaxun Yang