Sebastien Bourdeauducq
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b75fb7f97c
|
csr/SRAM: support for writes with memory widths larger than bus words
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2013-03-09 00:50:57 +01:00 |
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Sebastien Bourdeauducq
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6fa30053bf
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fhdl/verilog: tristate outputs are always wire
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2013-03-06 11:30:52 +01:00 |
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Sebastien Bourdeauducq
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9b4ca987e0
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bus/csr: support memories with larger word width than the bus (read only)
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2013-03-03 19:27:13 +01:00 |
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Sebastien Bourdeauducq
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bb5ee8d3bd
|
fhdl/autofragment: bugfixes + add auto_attr
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2013-03-03 17:53:06 +01:00 |
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Sebastien Bourdeauducq
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cc8118d35c
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fhdl/autofragment: FModule
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2013-03-02 23:30:54 +01:00 |
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Sebastien Bourdeauducq
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d2491828a4
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csr/SRAM: prefix page register with memory name
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2013-03-01 12:06:12 +01:00 |
|
Sebastien Bourdeauducq
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c10622f5e2
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fhdl/verilog: insert reset before listing signals
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2013-02-27 18:10:04 +01:00 |
|
Sebastien Bourdeauducq
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d2cbc70190
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bank/description: memprefix
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2013-02-25 23:14:15 +01:00 |
|
Sebastien Bourdeauducq
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a81781f589
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fhdl/specials: allow setting memory name
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2013-02-25 23:14:03 +01:00 |
|
Sebastien Bourdeauducq
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425de02f42
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uio/ioo: fix specials
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2013-02-25 23:13:38 +01:00 |
|
Sebastien Bourdeauducq
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55ab01f928
|
fhdl/specials/Instance: _printintbool -> verilog_printexpr
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2013-02-24 13:08:01 +01:00 |
|
Sebastien Bourdeauducq
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a878db1e3c
|
genlib: clock domain crossing elements
|
2013-02-23 19:03:35 +01:00 |
|
Sebastien Bourdeauducq
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7c4e6c35e5
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fhdl/verilog: support special lowering and overrides
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2013-02-23 19:03:16 +01:00 |
|
Sebastien Bourdeauducq
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f9acee4e68
|
corelogic -> genlib
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2013-02-22 23:19:37 +01:00 |
|
Sebastien Bourdeauducq
|
38664d6e16
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fhdl: inline synthesis directive support
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2013-02-22 19:10:02 +01:00 |
|
Sebastien Bourdeauducq
|
49cfba50fa
|
New 'specials' API
|
2013-02-22 17:56:35 +01:00 |
|
Sebastien Bourdeauducq
|
1b18194b1d
|
fhdl: TSTriple
|
2013-02-19 17:26:02 +01:00 |
|
Sebastien Bourdeauducq
|
dc93a231c6
|
fhdl: tristate support
|
2013-02-15 00:17:24 +01:00 |
|
Sebastien Bourdeauducq
|
63d399b6ad
|
fhdl/autofragment: from_attributes
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2013-02-11 18:34:01 +01:00 |
|
Sebastien Bourdeauducq
|
92b67df41c
|
sim: default runner to Icarus Verilog
|
2013-02-09 17:04:53 +01:00 |
|
Sebastien Bourdeauducq
|
bd6856ba7a
|
flow/perftools: finish removing ActorNode
|
2013-02-09 17:03:48 +01:00 |
|
Sebastien Bourdeauducq
|
473fd20f8c
|
fhdl/structure: store clock domain name
|
2013-01-24 13:49:49 +01:00 |
|
Sebastien Bourdeauducq
|
3201554f76
|
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
|
2013-01-23 15:13:06 +01:00 |
|
Sebastien Bourdeauducq
|
314a6c7743
|
corelogic: complex arithmetic support
|
2013-01-05 14:18:36 +01:00 |
|
Sebastien Bourdeauducq
|
badba89686
|
fhdl: support nested statement lists
|
2013-01-05 14:18:15 +01:00 |
|
Sebastien Bourdeauducq
|
47f5fc70e4
|
pytholite: fix bug with constant assignment to register
|
2012-12-19 16:21:57 +01:00 |
|
Sebastien Bourdeauducq
|
9c65402fda
|
pytholite: prune unused registers
|
2012-12-19 16:03:05 +01:00 |
|
Sebastien Bourdeauducq
|
3fae6c8f03
|
Do not use super()
|
2012-12-18 14:54:33 +01:00 |
|
Sebastien Bourdeauducq
|
b06fbdedd6
|
fhdl/tools: bitreverse
|
2012-12-14 23:56:16 +01:00 |
|
Sebastien Bourdeauducq
|
1f350adf14
|
actorlib/sim/SimActor: do not drive busy low when generator yields None
|
2012-12-14 23:56:03 +01:00 |
|
Sebastien Bourdeauducq
|
a67f483f0f
|
Token: support idle_wait
|
2012-12-14 19:16:22 +01:00 |
|
Sebastien Bourdeauducq
|
6f99241585
|
Move Token to migen.flow.transactions
|
2012-12-14 15:55:38 +01:00 |
|
Sebastien Bourdeauducq
|
28b4d99d31
|
replace some forgotten is_abstract()
|
2012-12-12 22:36:45 +01:00 |
|
Sebastien Bourdeauducq
|
a7227d7d2b
|
Remove ActorNode
|
2012-12-12 22:20:48 +01:00 |
|
Sebastien Bourdeauducq
|
8163ed4828
|
Merge branch 'master' of github.com:milkymist/migen
|
2012-12-06 20:57:30 +01:00 |
|
Sebastien Bourdeauducq
|
483b821342
|
fhdl/structure: do not create Signal in Instance when parameter is int
|
2012-12-06 20:56:46 +01:00 |
|
Sebastien Bourdeauducq
|
280a87ea69
|
elsewhere: do not create interface in default param
|
2012-12-06 17:34:48 +01:00 |
|
Sebastien Bourdeauducq
|
62187aa23d
|
migen/bank: do not create interface in default param
|
2012-12-06 17:28:28 +01:00 |
|
Sebastien Bourdeauducq
|
c3fdf42825
|
bus/csr: add SRAM
|
2012-12-06 17:16:17 +01:00 |
|
Sebastien Bourdeauducq
|
e89c66bf14
|
bank/csrgen: interface -> bus
|
2012-12-06 17:15:34 +01:00 |
|
Sebastien Bourdeauducq
|
273d9d285b
|
bank/description: define reset value of read signal
|
2012-12-05 16:40:44 +01:00 |
|
Sebastien Bourdeauducq
|
34ce934809
|
actorlib/sim: drive busy high until generator is finished
|
2012-12-05 16:40:12 +01:00 |
|
Sebastien Bourdeauducq
|
4bcb39699b
|
bus/wishbone/sram: accept memories < 32 bits
|
2012-12-01 13:04:22 +01:00 |
|
Sebastien Bourdeauducq
|
523816982a
|
bus/wishbone: add SRAM
|
2012-12-01 12:59:09 +01:00 |
|
Sebastien Bourdeauducq
|
adb1565d7a
|
pytholite: fix bit width of selection signal
|
2012-11-30 17:07:32 +01:00 |
|
Sebastien Bourdeauducq
|
cfb23c442f
|
pytholite: support signed registers
|
2012-11-30 17:07:12 +01:00 |
|
Sebastien Bourdeauducq
|
7093939309
|
corelogic/roundrobin: fix request width (again)
|
2012-11-29 23:47:51 +01:00 |
|
Sebastien Bourdeauducq
|
31c722f993
|
corelogic/roundrobin: fix request width
|
2012-11-29 23:47:08 +01:00 |
|
Sebastien Bourdeauducq
|
70e97e0456
|
Fix various errors from new bitwidth/signedness system conversion
|
2012-11-29 23:36:55 +01:00 |
|
Sebastien Bourdeauducq
|
261166d92b
|
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
|
2012-11-29 22:59:54 +01:00 |