Sebastien Bourdeauducq
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34d8ae3c11
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flow: perftools
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2012-06-20 21:59:17 +02:00 |
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Sebastien Bourdeauducq
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9a38c47048
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examples/dataflow/structuring: test Cast
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2012-06-20 18:29:03 +02:00 |
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Sebastien Bourdeauducq
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6fac3f027f
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examples/dataflow: structuring test
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2012-06-20 18:25:01 +02:00 |
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Sebastien Bourdeauducq
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1576cb0950
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actorlib/control: simplify + fix
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2012-06-17 21:19:47 +02:00 |
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Sebastien Bourdeauducq
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e1ff776752
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remove spurious module
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2012-06-17 21:19:22 +02:00 |
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Sebastien Bourdeauducq
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4873cfe1a7
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flow/plumbing: Combinator/Splitter should not inherit CombinatorialActor
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2012-06-17 13:45:18 +02:00 |
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Sebastien Bourdeauducq
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21eb17fc36
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examples/flow: Fibonacci demo
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2012-06-16 22:41:34 +02:00 |
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Sebastien Bourdeauducq
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f7cac15b34
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examples/flow/arithmetic: cleanup
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2012-06-16 22:37:25 +02:00 |
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Sebastien Bourdeauducq
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c1450daa93
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flow: insert splitters
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2012-06-16 21:23:42 +02:00 |
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Sebastien Bourdeauducq
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5c139511e8
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examples/flow/arithmetic: simulate
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2012-06-16 19:23:59 +02:00 |
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Sebastien Bourdeauducq
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bde8361e19
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flow: insert combinators and infer plumbing layout
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2012-06-16 17:30:54 +02:00 |
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Sebastien Bourdeauducq
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da522cd58d
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Abstract actor graphs
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2012-06-15 17:52:19 +02:00 |
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Sebastien Bourdeauducq
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b14be4c8a3
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actorlib: ASMI sequential reader
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2012-06-12 21:04:47 +02:00 |
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Sebastien Bourdeauducq
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3a58916a4f
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examples/dataflow/dma: refactor
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2012-06-12 19:55:57 +02:00 |
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Sebastien Bourdeauducq
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973c00938d
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Reorganize examples folder
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2012-06-12 17:49:50 +02:00 |
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Sebastien Bourdeauducq
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8a23451237
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PureSimulable
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2012-06-12 17:08:56 +02:00 |
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Sebastien Bourdeauducq
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a591510189
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ASMI simulation models
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2012-06-12 16:57:00 +02:00 |
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Sebastien Bourdeauducq
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b7a84b3750
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wishbone: base TargetModel class
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2012-06-10 17:05:10 +02:00 |
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Sebastien Bourdeauducq
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ec501e7797
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bus/wishbone: target model
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2012-06-10 16:40:33 +02:00 |
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Sebastien Bourdeauducq
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5964df62db
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examples/dataflow: only import nx when needed
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2012-06-08 22:54:04 +02:00 |
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Sebastien Bourdeauducq
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009f26bb9d
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flow/network: refactor graph
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2012-06-08 22:49:49 +02:00 |
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Sebastien Bourdeauducq
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f86170e349
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actorlib: WB writer simulation OK
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2012-06-08 21:31:57 +02:00 |
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Sebastien Bourdeauducq
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356051e8a8
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actorlib: WB reader simulation OK
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2012-06-08 21:31:05 +02:00 |
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Sebastien Bourdeauducq
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910c7806cf
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actorlib: generator-based generic simulation actor
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2012-06-08 17:54:03 +02:00 |
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Sebastien Bourdeauducq
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d280723618
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examples/fir: print Verilog source
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2012-06-08 14:00:49 +02:00 |
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Sebastien Bourdeauducq
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b00e8fa826
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examples/fir: plot input and output signals
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2012-06-07 23:20:59 +02:00 |
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Sebastien Bourdeauducq
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081b658e2d
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Update copyright notices
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2012-03-23 16:41:30 +01:00 |
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Sebastien Bourdeauducq
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f6e76ae198
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doc: more examples and comments
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2012-03-10 19:38:39 +01:00 |
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Sebastien Bourdeauducq
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57a87b3316
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examples: FIR filter simulation
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2012-03-08 20:49:36 +01:00 |
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Sebastien Bourdeauducq
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f4adb0fe9c
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examples: remove outdated wb_intercon simulation
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2012-03-08 18:17:56 +01:00 |
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Sebastien Bourdeauducq
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ab800fa2ed
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bus: generic transaction model
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2012-03-08 18:14:06 +01:00 |
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Sebastien Bourdeauducq
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59a57e7a76
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examples: small cleanup
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2012-03-08 15:55:02 +01:00 |
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Sebastien Bourdeauducq
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98e96b3952
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sim: make initialization cycle optional (selectable by function attribute)
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2012-03-06 19:43:59 +01:00 |
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Sebastien Bourdeauducq
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8160ced2e9
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sim: memory access
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2012-03-06 19:29:39 +01:00 |
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Sebastien Bourdeauducq
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6f829c7afc
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sim: support for signed numbers
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2012-03-06 16:46:18 +01:00 |
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Sebastien Bourdeauducq
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9da512dbf5
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sim: VCD generation
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2012-03-06 15:26:04 +01:00 |
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Sebastien Bourdeauducq
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22b3c11b93
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sim: clean startup/shutdown
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2012-03-06 15:00:02 +01:00 |
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Sebastien Bourdeauducq
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aac9752558
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sim: basic functionality working
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2012-03-05 20:31:41 +01:00 |
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Sebastien Bourdeauducq
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ca7056b07f
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fhdl: support forwarding of bidirectional signals from instance ports
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2012-02-16 18:34:32 +01:00 |
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Sebastien Bourdeauducq
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ef7aea0f31
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bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
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2012-02-15 18:23:31 +01:00 |
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Sebastien Bourdeauducq
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91e279ee04
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bank/csrgen: use new bus API
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2012-02-15 16:42:17 +01:00 |
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Sebastien Bourdeauducq
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0493212124
|
bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
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2012-02-15 16:30:16 +01:00 |
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Sebastien Bourdeauducq
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0c214b484e
|
Use double quotes for all strings
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2012-02-14 13:12:43 +01:00 |
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Sebastien Bourdeauducq
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3a2a0c4dd8
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bank: support registers larger than the bus word width
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2012-02-06 16:15:27 +01:00 |
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Sebastien Bourdeauducq
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f3ddfffc47
|
bank: refactoring
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2012-02-06 13:55:50 +01:00 |
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Sebastien Bourdeauducq
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3143608e0a
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examples/wb_intercon: update to new APIs
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2012-01-28 23:18:21 +01:00 |
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Sebastien Bourdeauducq
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685b5eb08f
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fhdl: support memory read enable
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2012-01-27 21:39:23 +01:00 |
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Sebastien Bourdeauducq
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5405a83ff9
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fhdl: memories working
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2012-01-27 20:22:17 +01:00 |
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Sebastien Bourdeauducq
|
076c171c7b
|
Use meaningful class names
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2012-01-20 23:07:32 +01:00 |
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Sebastien Bourdeauducq
|
a1043d11c0
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examples/corelogic_conv: use two dividers
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2012-01-16 19:38:39 +01:00 |