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Author SHA1 Message Date
Florent Kermarrec d3ea912339 CHANGES: Update. 2024-02-22 10:24:35 +01:00
Florent Kermarrec fe0363da25 CHANGES.md: Update. 2024-02-13 16:04:13 +01:00
Florent Kermarrec f36e7d379a CHANGES.md: Update. 2024-02-12 17:21:42 +01:00
Florent Kermarrec e44631294a CHANGES.md: Update. 2024-02-01 08:34:17 +01:00
Florent Kermarrec a3904ac26d CHANGES.md: Update. 2024-01-30 09:51:05 +01:00
Florent Kermarrec c31ec79981 CHANGES.md: Update. 2024-01-23 16:02:11 +01:00
Florent Kermarrec 8aa5958fb7 cores/cpu: Add intitial gowin_ae350 support. 2024-01-11 13:11:56 +01:00
Florent Kermarrec c61d2de13b CHANGES.md: Update. 2024-01-04 15:37:58 +01:00
Florent Kermarrec 67cfcadf79 setup.py/CHANGES.md: Prepare 2023.12 release. 2023-12-25 15:36:10 +01:00
Florent Kermarrec 040b554022 CHANGES.md: Update. 2023-12-20 16:11:12 +01:00
Florent Kermarrec 23fbd1b334 CHANGES.md: Update. 2023-12-20 16:10:03 +01:00
Florent Kermarrec 4721029e58 CHANGES.md: Update. 2023-12-20 15:25:14 +01:00
Florent Kermarrec fadea1d31b CHANGES.md: Update. 2023-12-20 08:08:42 +01:00
Florent Kermarrec 048c42820c setup.py: Switch minimum Python version to 3.7 (To allow more than 255 arguments in functions). 2023-12-19 10:32:12 +01:00
Florent Kermarrec 0c3cda3ee8 CHANGES.md: Update. 2023-12-19 10:09:44 +01:00
Florent Kermarrec b6e89c646e CHANGES: Update. 2023-12-14 11:08:55 +01:00
Florent Kermarrec 8d6120c476 CHANGES: Update. 2023-12-08 12:11:37 +01:00
Florent Kermarrec afaeca98ce CHANGES.md: Update. 2023-12-07 16:33:32 +01:00
Florent Kermarrec 4353135f02 CHANGES: Update. 2023-11-16 13:47:17 +01:00
Florent Kermarrec 639c899838 CHANGES.md: Update. 2023-11-10 10:27:37 +01:00
Florent Kermarrec c419706856 CHANGES: Update. 2023-11-09 15:24:40 +01:00
Florent Kermarrec 6598fe9c12 cores/cpu: Add KianV CPU (RV32IMA) initial support. 
litex_sim --cpu-type=kianv:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2023 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Nov  8 2023 11:14:03
 BIOS CRC passed (6984e675)

 LiteX git sha1: c1e4b3a8

--=============== SoC ==================--
CPU:		KianV-STANDARD @ 1MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128.0KiB
SRAM:		8.0KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> ident
Ident: LiteX Simulation 2023-11-08 11:14:00
litex>
 2023-11-08 11:37:22 +01:00
Florent Kermarrec 9b8a5b6385 CHANGES: Update. 2023-10-30 19:40:42 +01:00
Florent Kermarrec fa629b782f CHANGES: Update. 2023-10-27 11:40:31 +02:00
Florent Kermarrec 69dc666177 CHANGES: Update. 2023-10-25 16:01:45 +02:00
Florent Kermarrec e426e78e31 CHANGES.md: Update. 2023-10-11 10:17:57 +02:00
Florent Kermarrec 0890bf4c1f CHANGES: Update. 2023-10-11 09:13:33 +02:00
Florent Kermarrec 5380df3994 CHANGES: Update. 2023-10-06 19:50:52 +02:00
Florent Kermarrec cd8218779e soc/cores/video/VideoFramebuffer: Add VTG/DMA synchronization when DMA is enabled to simplify use. 2023-10-06 10:11:34 +02:00
Florent Kermarrec 98eb27df52 CHANGES: Update. 2023-10-05 08:25:52 +02:00
Florent Kermarrec f5b7c0d88e CHANGES: Update. 2023-09-26 13:49:19 +02:00
Florent Kermarrec 04a33c5ddb CHANGES: Update. 2023-09-18 09:09:45 +02:00
Florent Kermarrec 8bd548d453 CHANGES.md: Start listing changes since 2023.08. 2023-09-18 09:02:05 +02:00
Florent Kermarrec a2c2c211c5 Changes.md: Release 2023.08. 2023-09-14 10:47:37 +02:00
Florent Kermarrec d165418719 CHANGES.md: Update. 2023-09-12 09:35:53 +02:00
Florent Kermarrec fbae6e8e37 CHANGES.md: Update. 2023-09-07 14:27:12 +02:00
Florent Kermarrec 57faa9102f CHANGES: Update. 2023-09-01 12:40:03 +02:00
Florent Kermarrec 9854c9f322 CHANGES: Update. 2023-08-30 18:11:11 +02:00
Florent Kermarrec 9528f89d45 CHANGES: Update. 2023-08-29 17:15:45 +02:00
Florent Kermarrec 70e52b76fa CHANGES: Update. 2023-08-28 16:04:43 +02:00
Florent Kermarrec 688dae0112 cores/spi: Add new SPIMMAP core allowing doing SPI accesses directly from MMAP. 
Implements a new SPIMMAP module, allowing accessing multiple SPI peripherals directly
from MMAP. It allows configurable SPI transactions: mode, bit order, and data width.

Developed and funded through a collaboration with MoTeC.

Example of integration:

# SPI MMAP ---------------------------------------------------------------------------------
spi_pads = Record([("clk", 1), ("cs_n", 8), ("mosi", 1), ("miso", 1)])
spi_mmap_tx_region = SoCRegion(origin=0x8000_0000, size=4096, cached=False)
spi_mmap_rx_region = SoCRegion(origin=0x8000_1000, size=4096, cached=False)
self.spi_mmap = SPIMMAP(
    pads          = spi_pads,
    data_width    = 32,
    sys_clk_freq  = sys_clk_freq,
    tx_origin     = spi_mmap_tx_region.origin,
    rx_origin     = spi_mmap_rx_region.origin,
    tx_fifo_depth = 32,
    rx_fifo_depth = 32,
)

self.bus.add_slave(name="spi_tx",
    slave  = self.spi_mmap.tx_mmap.bus,
    region = spi_mmap_tx_region,
)
self.bus.add_slave(name="spi_rx",
    slave  = self.spi_mmap.rx_mmap.bus,
    region = spi_mmap_rx_region,
)
self.irq.add("spi_mmap", use_loc_if_exists=True)


Example of use from CPU C firmware:

/* SPI TX Offsets */
#define SPI_TX_CTRL_ENABLE    (1 << 0)
#define SPI_TX_CTRL_THRESHOLD (1 << 16)

#define SPI_TX_STAT_ONGOING   (1 << 0)
#define SPI_TX_STAT_EMPTY     (1 << 1)
#define SPI_TX_STAT_FULL      (1 << 2)
#define SPI_TX_STAT_LEVEL     (1 << 16)

/* SPI RX Offsets */
#define SPI_RX_CTRL_ENABLE    (1 << 0)
#define SPI_RX_CTRL_THRESHOLD (1 << 16)

#define SPI_RX_STAT_ONGOING   (1 << 0)
#define SPI_RX_STAT_EMPTY     (1 << 1)
#define SPI_RX_STAT_FULL      (1 << 2)
#define SPI_RX_STAT_LEVEL     (1 << 16)

/* SPI TX/RX Engine */
#define SPI_TX_RX_ENGINE_ENABLE (1 << 0)

/* SPI SLOT Offsets */
#define SPI_SLOT_ENABLE   (1 <<  0)
#define SPI_SLOT_MODE     (1 <<  1)
#define SPI_SLOT_LENGTH   (1 <<  3)
#define SPI_SLOT_BITORDER (1 <<  5)
#define SPI_SLOT_LOOPBACK (1 <<  6)
#define SPI_SLOT_DIVIDER  (1 << 16)

/* SPI SLOT Values */
#define SPI_SLOT_MODE_0 0b00
#define SPI_SLOT_MODE_3 0b11

#define SPI_SLOT_LENGTH_32B 0b00
#define SPI_SLOT_LENGTH_16B 0b01
#define SPI_SLOT_LENGTH_8B  0b10

#define SPI_SLOT_BITORDER_MSB_FIRST 0b0
#define SPI_SLOT_BITORDER_LSB_FIRST 0b1

#define SPI_SLOT_EV_TX (1 << 0)
#define SPI_SLOT_EV_RX (1 << 1)


/* Test SPI with various length (BE) */
void test_spi_length_8_16_32(void) {
	volatile unsigned char  *spi_tx_8  = (unsigned char  *)SPI_TX_BASE;
	volatile unsigned short *spi_tx_16 = (unsigned short *)SPI_TX_BASE;
	volatile unsigned int   *spi_tx_32 = (unsigned int   *)SPI_TX_BASE;

	volatile unsigned char  *spi_rx_8  = (unsigned char  *)SPI_RX_BASE;
	volatile unsigned short *spi_rx_16 = (unsigned short *)SPI_RX_BASE;
	volatile unsigned int   *spi_rx_32 = (unsigned int   *)SPI_RX_BASE;

	int errors = 0;

	printf("Test SPI with various length (BE): 8, 16 and 32-bit...\n");

	/* Configure Slots */
	spi_mmap_ctrl_slot_control0_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_0 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								  4 * SPI_SLOT_DIVIDER
	);
	spi_mmap_ctrl_slot_control1_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_0 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								  4 * SPI_SLOT_DIVIDER
	);
	spi_mmap_ctrl_slot_control2_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_0 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								  4 * SPI_SLOT_DIVIDER
	);
	spi_mmap_ctrl_slot_control3_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_0 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								  4 * SPI_SLOT_DIVIDER
	);

	/* Enable SPI Engine */
	spi_mmap_tx_rx_engine_control_write(1 * SPI_TX_RX_ENGINE_ENABLE);

	/* TX 8-bit transfers */
	spi_tx_8[0]  = 0x5a;
	spi_tx_8[4]  = 0x01;
	spi_tx_8[8]  = 0x5a;
	spi_tx_8[12] = 0x01;

	/* TX 16-bit transfers */
	spi_tx_16[0] = 0x5aa5;
	spi_tx_16[2] = 0x0102;
	spi_tx_16[4] = 0x5aa5;
	spi_tx_16[6] = 0x0102;

	/* TX 32-bit transfers */
	spi_tx_32[0] = 0x5aa55aa5;
	spi_tx_32[1] = 0x01020304;
	spi_tx_32[2] = 0x5aa55aa5;
	spi_tx_32[3] = 0x01020304;

	/* Small delay */
	busy_wait(1);

	/* Read RX 8-bit transfers */
	if (spi_rx_8[ 0] != 0x5a)
		errors++;
	if (spi_rx_8[ 4] != 0x01)
		errors++;
	if (spi_rx_8[ 8] != 0x5a)
		errors++;
	if (spi_rx_8[12] != 0x01)
		errors++;

	/* Read RX 16-bit transfers */
	if (spi_rx_16[0] != 0x5aa5)
		errors++;
	if (spi_rx_16[2] != 0x0102)
		errors++;
	if (spi_rx_16[4] != 0x5aa5)
		errors++;
	if (spi_rx_16[6] != 0x0102)
		errors++;

	/* Read RX 32-bit tranfers */
	if (spi_rx_32[0] != 0x5aa55aa5)
		errors++;
	if (spi_rx_32[1] != 0x01020304)
		errors++;
	if (spi_rx_32[2] != 0x5aa55aa5)
		errors++;
	if (spi_rx_32[3] != 0x01020304)
		errors++;

	/* Disable SPI Engine */
	spi_mmap_tx_rx_engine_control_write(0 * SPI_TX_RX_ENGINE_ENABLE);

	/* Result */
	printf("errors: %d\n", errors);
}

/* Test SPI with various clk divider */
void test_spi_clk_divider(void) {
	volatile unsigned int *spi_tx_32 = (unsigned int *)SPI_TX_BASE;
	volatile unsigned int *spi_rx_32 = (unsigned int *)SPI_RX_BASE;

	int errors = 0;

	printf("Test SPI with various clk divider: 4, 8, 16 and 32...\n");

	/* Configure Slots */
	spi_mmap_ctrl_slot_control0_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_0 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								  4 * SPI_SLOT_DIVIDER
	);
	spi_mmap_ctrl_slot_control1_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_0 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								  8 * SPI_SLOT_DIVIDER
	);
	spi_mmap_ctrl_slot_control2_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_0 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								 16 * SPI_SLOT_DIVIDER
	);
	spi_mmap_ctrl_slot_control3_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_0 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								 32 * SPI_SLOT_DIVIDER
	);

	/* Enable SPI Engine */
	spi_mmap_tx_rx_engine_control_write(1 * SPI_TX_RX_ENGINE_ENABLE);

	/* TX 32-bit transfers */
	spi_tx_32[0] = 0x01020304;
	spi_tx_32[1] = 0x5aa55aa5;
	spi_tx_32[2] = 0x01020304;
	spi_tx_32[3] = 0x5aa55aa5;

	/* Small delay */
	busy_wait(1);

	/* Read RX 32-bit tranfers */
	if (spi_rx_32[0] != 0x01020304)
		errors++;
	if (spi_rx_32[1] != 0x5aa55aa5)
		errors++;
	if (spi_rx_32[2] != 0x01020304)
		errors++;
	if (spi_rx_32[3] != 0x5aa55aa5)
		errors++;

	/* Disable SPI Engine */
	spi_mmap_tx_rx_engine_control_write(0 * SPI_TX_RX_ENGINE_ENABLE);

	/* Result */
	printf("errors: %d\n", errors);
}

/* Test SPI with various SPI modes */
void test_spi_modes(void) {
	volatile unsigned int *spi_tx_32 = (unsigned int *)SPI_TX_BASE;
	volatile unsigned int *spi_rx_32 = (unsigned int *)SPI_RX_BASE;

	int errors = 0;

	printf("Test SPI with various SPI modes: 0 and 3...\n");

	/* Configure Slots */
	spi_mmap_ctrl_slot_control0_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_0 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								  4 * SPI_SLOT_DIVIDER
	);
	spi_mmap_ctrl_slot_control1_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_3 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								  4 * SPI_SLOT_DIVIDER
	);

	/* Enable SPI Engine */
	spi_mmap_tx_rx_engine_control_write(1 * SPI_TX_RX_ENGINE_ENABLE);

	/* TX 32-bit transfers */
	spi_tx_32[0] = 0x5aa55aa5;
	spi_tx_32[1] = 0x5aa55aa5;

	/* Small delay */
	busy_wait(1);

	/* Read RX 32-bit tranfers */
	if (spi_rx_32[0] != 0x5aa55aa5)
		errors++;
	if (spi_rx_32[1] != 0x5aa55aa5)
		errors++;

	/* Disable SPI Engine */
	spi_mmap_tx_rx_engine_control_write(0 * SPI_TX_RX_ENGINE_ENABLE);

	/* Result */
	printf("errors: %d\n", errors);
}

/* Test SPI with various bitorders */
void test_spi_bitorders(void) {
	volatile unsigned int *spi_tx_32 = (unsigned int *)SPI_TX_BASE;
	volatile unsigned int *spi_rx_32 = (unsigned int *)SPI_RX_BASE;

	int errors = 0;

	printf("Test SPI with various bitorders: MSB and LSB first...\n");

	/* Configure Slots */
	spi_mmap_ctrl_slot_control0_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_0 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								  4 * SPI_SLOT_DIVIDER
	);
	spi_mmap_ctrl_slot_control1_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_0 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_LSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								  4 * SPI_SLOT_DIVIDER
	);

	/* Enable SPI Engine */
	spi_mmap_tx_rx_engine_control_write(1 * SPI_TX_RX_ENGINE_ENABLE);

	/* TX 32-bit transfers */
	spi_tx_32[0] = 0xff000000;
	spi_tx_32[1] = 0xff000000;

	/* Small delay */
	busy_wait(1);

	/* Read RX 32-bit tranfers */
	if (spi_rx_32[0] != 0xff000000)
		errors++;
	if (spi_rx_32[1] != 0xff000000)
		errors++;

	/* Disable SPI Engine */
	spi_mmap_tx_rx_engine_control_write(0 * SPI_TX_RX_ENGINE_ENABLE);

	/* Result */
	printf("errors: %d\n", errors);
}

/* Test SPI TX/RX levels */
void test_spi_tx_rx_levels(void) {
	volatile unsigned int *spi_tx_32 = (unsigned int *)SPI_TX_BASE;
	volatile unsigned int *spi_rx_32 = (unsigned int *)SPI_RX_BASE;

	int i;
	int errors = 0;
	int pattern;

	printf("Test SPI TX/RX levels...\n");

	/* Configure Slots */
	spi_mmap_ctrl_slot_control0_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_0 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								128 * SPI_SLOT_DIVIDER
	);

	/* Enable SPI Engine */
	spi_mmap_tx_rx_engine_control_write(1 * SPI_TX_RX_ENGINE_ENABLE);

	/* TX 32-bit transfers */
	pattern = 0x00000001;
	for (i=0; i<16; i++){
		if ((spi_mmap_ctrl_tx_status_read() >> 16) != i)
			errors++;
		spi_tx_32[0] = pattern;
	}

	/* Small delay */
	busy_wait(1);

	/* Read RX 32-bit tranfers */
	for (i=0; i<16; i++){
		pattern = spi_rx_32[0];
		if ((spi_mmap_ctrl_rx_status_read() >> 16) != (16-1-i))
			errors++;
	}

	if ((spi_mmap_ctrl_tx_status_read() >> 16) != 0)
		errors++;
	if ((spi_mmap_ctrl_rx_status_read() >> 16) != 0)
		errors++;

	/* Disable SPI Engine */
	spi_mmap_tx_rx_engine_control_write(0 * SPI_TX_RX_ENGINE_ENABLE);

	/* Result */
	printf("errors: %d\n", errors);
}

/* Test SPI TX/RX IRQs */
void test_spi_tx_rx_irqs(void) {
	volatile unsigned int *spi_tx_32 = (unsigned int *)SPI_TX_BASE;
	volatile unsigned int *spi_rx_32 = (unsigned int *)SPI_RX_BASE;

	int errors = 0;
	int data __attribute__((unused));

	printf("Test SPI TX/RX IRQs...\n");

	/* Configure Slots */
	spi_mmap_ctrl_slot_control0_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_0 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								128 * SPI_SLOT_DIVIDER
	);

	/* Enable TX/RX EventManager */
	spi_mmap_ev_enable_write(0);
	spi_mmap_ev_pending_write(spi_mmap_ev_pending_read());
	spi_mmap_ev_enable_write(SPI_SLOT_EV_TX | SPI_SLOT_EV_RX);

	/* Enable SPI Engine */
	spi_mmap_tx_rx_engine_control_write(1 * SPI_TX_RX_ENGINE_ENABLE);

	/* TX 32-bit transfers */
	spi_tx_32[0] = 0x00000001;

	/* Small delay */
	busy_wait(1);

	/* Verify TX/RX events */
	if (spi_mmap_ev_pending_read() != (SPI_SLOT_EV_TX | SPI_SLOT_EV_RX))
		errors++;

	/* Read RX 32-bit tranfers */
	data = spi_rx_32[0];

	/* Clear events */
	spi_mmap_ev_pending_write(spi_mmap_ev_pending_read());

	/* Verify TX/RX events */
	if (spi_mmap_ev_pending_read() != 0)
		errors++;

	/* Disable SPI Engine */
	spi_mmap_tx_rx_engine_control_write(0 * SPI_TX_RX_ENGINE_ENABLE);

	/* Result */
	printf("errors: %d\n", errors);
}


/* Test SPI Back-to-Back */
void test_spi_back_to_back(void) {
	volatile unsigned int *spi_tx_32 = (unsigned int *)SPI_TX_BASE;
	volatile unsigned int *spi_rx_32 = (unsigned int *)SPI_RX_BASE;

	int errors = 0;

	printf("Test SPI Back-to-Back...\n");

	/* Configure Slots */
	spi_mmap_ctrl_slot_control0_write(
								  1 * SPI_SLOT_ENABLE   |
					SPI_SLOT_MODE_0 * SPI_SLOT_MODE     |
				SPI_SLOT_LENGTH_32B * SPI_SLOT_LENGTH   |
		SPI_SLOT_BITORDER_MSB_FIRST * SPI_SLOT_BITORDER |
								  1 * SPI_SLOT_LOOPBACK |
								  8 * SPI_SLOT_DIVIDER
	);

	/* Enable SPI Engine */
	spi_mmap_tx_rx_engine_control_write(1 * SPI_TX_RX_ENGINE_ENABLE);

	/* TX 32-bit transfers */
	spi_tx_32[0] = 0x00000001;
	spi_tx_32[0] = 0x00000002;

	/* Small delay */
	busy_wait(1);

	/* Read RX 32-bit tranfers */
	if (spi_rx_32[0] != 0x00000001)
		errors++;
	if (spi_rx_32[0] != 0x00000002)
		errors++;

	/* Disable SPI Engine */
	spi_mmap_tx_rx_engine_control_write(0 * SPI_TX_RX_ENGINE_ENABLE);

	/* Result */
	printf("errors: %d\n", errors);
}
 2023-08-04 17:44:54 +02:00
Florent Kermarrec 036193d046 CHANGES: Update. 2023-08-04 16:08:00 +02:00
Florent Kermarrec 87e2456274 CHANGES.md: Update. 2023-07-31 18:00:43 +02:00
Florent Kermarrec b2e4b22145 soc/add_pcie: Add with_ptm parameter and update CHANGES. 2023-07-30 15:12:01 +02:00
Florent Kermarrec 74401d6f03 CHANGES: Update. 2023-07-27 13:58:45 +02:00
Florent Kermarrec 66b44ecd60 soc/add_uart: Fix stub behavior (sink/source swap), thanks @zyp. 2023-07-26 12:26:16 +02:00
Florent Kermarrec 0f1fdea893 build/xilinx/vivado: Also generate design checkpoint after synthesis and placement. 
This help exploring/constraining complex designs by using Vivado GUI and design checkpoint.
 2023-07-21 19:53:28 +02:00
Florent Kermarrec 35cd744adc CHANGES: Update. 2023-07-21 15:16:42 +02:00
Florent Kermarrec 330d61d2bd soc/add_pcie: Remove MSI workaround on Ultrascale(+) now that root cause is understood/fixed (thanks @smunaut). 2023-07-21 14:50:38 +02:00
Florent Kermarrec aae15737cd CHANGES: Update. 2023-07-20 16:30:48 +02:00