Commit Graph

70 Commits

Author SHA1 Message Date
Florent Kermarrec e011f9378f use sets for leave_out 2015-07-05 22:49:23 +02:00
Florent Kermarrec 04c64eb1d8 litesata/example_designs: fix core generation (RAID introduced some changes on the PHY) 2015-06-26 00:20:58 +02:00
Olof Kindgren 52e6bf6987 litesata/test: Add missing dependency on scrambler in bist_tb 2015-06-26 01:20:25 +02:00
Olof Kindgren ffb6081720 litesata/example_designs: Add missing clock in phy instantiation 2015-06-26 01:20:25 +02:00
Florent Kermarrec a1f7ecc8c5 litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :) 2015-06-10 12:15:59 +02:00
Florent Kermarrec 571ce5791a litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization
self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.
2015-06-10 12:14:48 +02:00
Sebastien Bourdeauducq d50bb8c55e litesata: more doc fixes 2015-05-26 14:13:13 +08:00
Sebastien Bourdeauducq 1e47cfce2b Merge branch 'master' of https://github.com/m-labs/misoc
Conflicts:
	misoclib/mem/litesata/doc/source/docs/frontend/index.rst
2015-05-26 13:57:26 +08:00
Sebastien Bourdeauducq a9da892b57 litesata: doc fixes 2015-05-26 13:54:31 +08:00
Florent Kermarrec 989d8a7c29 liteata: fix spelling & mistakes in doc 2015-05-26 07:37:09 +02:00
Florent Kermarrec eb922f6ddc litesata: rework frontend doc and add striping, mirroring 2015-05-25 14:04:37 +02:00
Florent Kermarrec 0d1a7b9315 litesata: add mirroring 2015-05-25 14:03:14 +02:00
Florent Kermarrec c3716296ae litesata/examples_designs: add striping 2015-05-25 14:02:02 +02:00
Florent Kermarrec 0d2db23603 litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink) 2015-05-25 13:55:15 +02:00
Florent Kermarrec 1bb5a05488 litesata: add striping module for use of multiple HDDs. 2015-05-23 14:12:20 +02:00
Florent Kermarrec 5daba9af68 litesata: do some cleanup and prepare for RAID 2015-05-23 14:08:56 +02:00
Florent Kermarrec d9b15e6ef6 cores: replace Timeout with new WaitTimer 2015-05-12 16:14:38 +02:00
Florent Kermarrec a99aa9c7fd uart: rename wishbone to bridge 2015-05-09 16:24:28 +02:00
Florent Kermarrec fb5397aa82 uart: remove litescope dependency for UARTWishboneBridge and remove frontend 2015-05-09 16:08:20 +02:00
Florent Kermarrec d9111f6a04 litesata: fix packets figure in frontend doc 2015-05-07 11:06:05 +02:00
Florent Kermarrec 5516a49696 litesata: add doc for frontend 2015-05-06 03:57:07 +02:00
Florent Kermarrec 6908ddbaf9 litesata: cleanup README/doc 2015-05-06 02:02:22 +02:00
Florent Kermarrec 7bdcbc94cd litesata: use (some) settings from vivado 2015.1, try to follow all ug476 recommendations to initialize GTX (...), remove automatic reset on top.
Works fine @ 3Gbps, still not working @6.0Gbps
2015-05-06 01:33:02 +02:00
Florent Kermarrec 3ebe877fd2 use similar names for wishbone bridges and move wishbone drivers to [core]/software 2015-05-02 16:22:30 +02:00
Florent Kermarrec c03c41eb77 litescope: rename host directory to software (to be coherent with others cores) 2015-05-01 20:45:02 +02:00
Florent Kermarrec 1281a463d6 litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
Florent Kermarrec 453279a7c8 litesata: cleanup link 2015-04-27 15:33:01 +02:00
Florent Kermarrec 1ef81c4d24 litesata: split hdd model (phy, link, transport, command & hdd) and update simulations 2015-04-27 14:51:03 +02:00
Florent Kermarrec ded3f22574 litesata: use new Migen modules from actorlib/packet.py (avoid duplications between cores) 2015-04-27 14:48:14 +02:00
Florent Kermarrec fe867ccf33 litesata: remove icarus_workaround.patch (obsolete) 2015-04-27 14:44:54 +02:00
Florent Kermarrec 5a930fe7cf lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file 2015-04-18 08:51:59 -04:00
Sebastien Bourdeauducq 958f149992 litesata/test: fix PYTHONPATH 2015-04-16 19:49:46 +08:00
Florent Kermarrec 2040727179 litesata: more pep8 (when convenient), should be almost OK 2015-04-13 16:09:04 +02:00
Florent Kermarrec 1f19e6ae92 litesata: pep8 (E265) 2015-04-13 15:58:58 +02:00
Florent Kermarrec c8bcbfb855 litesata: pep8 (E261, E271) 2015-04-13 15:51:17 +02:00
Florent Kermarrec 2e5501933a litesata: pep8 (W292) 2015-04-13 15:44:52 +02:00
Florent Kermarrec ea67080462 litesata: pep8 (E225) 2015-04-13 15:44:04 +02:00
Florent Kermarrec a9b42161c0 litesata: pep8 (E222) 2015-04-13 15:29:34 +02:00
Florent Kermarrec 77cdb953ad litesata: pep8 (E401) 2015-04-13 15:27:36 +02:00
Florent Kermarrec 8f7751e412 litesata: pep8 (E203) 2015-04-13 15:25:40 +02:00
Florent Kermarrec 61fa72b655 litesata: pep8 (E231) 2015-04-13 15:19:34 +02:00
Florent Kermarrec d0c5bd377a litesata: pep8 (E302) 2015-04-13 15:12:39 +02:00
Florent Kermarrec 808e1fe866 litesata: pep8 (replace tabs with spaces) 2015-04-13 14:59:00 +02:00
Florent Kermarrec ea613cd8ee litesata: update build core target generation 2015-04-09 00:00:25 +02:00
Florent Kermarrec 03aa972bb6 lite*: finish ModuleTransformer adaptations (need to be tested on board) 2015-04-08 23:27:22 +02:00
Robert Jordens 66f8dcbfaf lite*: adapt to new ModuleTransformer semantics
NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
2015-04-04 19:17:24 +08:00
Florent Kermarrec 60124be293 adapt LiteSATA to new SoC 2015-04-01 22:52:19 +02:00
Sebastien Bourdeauducq 6e2a662dd7 litesata: adapt to new SoC API 2015-04-01 17:37:53 +08:00
Florent Kermarrec 9107710f03 litexxx cores: use default baudrate of 115200 for all tests 2015-03-20 12:22:53 +01:00
Florent Kermarrec 236ea0f572 liteeth: use bios ip_address in example designs 2015-03-18 18:18:43 +01:00