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47 Commits

Author SHA1 Message Date
Florent Kermarrec 63b8797978 liteeth: move mac to core 2015-05-02 16:22:35 +02:00
Sebastien Bourdeauducq 1d9771f574 spiflash: use SoC defines, add write_to_flash function 2015-04-27 13:42:32 +08:00
Florent Kermarrec 0b1a2e1022 liteeth: do MII/GMII detection in gateware for gmii_mii phy 2015-04-26 18:08:07 +02:00
Florent Kermarrec 93de581931 soc: add shadow_address parameter 
When don't necessary want to have shadow memories and be able to start CSR at address 0x00000000(for example with an X86 CPU)
 2015-04-17 13:42:29 +02:00
Florent Kermarrec 2ccb5655c9 global: more pep8 
we will have to continue the work... volunteers are welcome :)
 2015-04-13 18:02:26 +02:00
Florent Kermarrec fc68d915c1 global: pep8 (E261, E271) 2015-04-13 17:16:12 +02:00
Florent Kermarrec f68423f423 global: pep8 (E302) 2015-04-13 16:47:22 +02:00
Florent Kermarrec d9e09707ae global: pep8 (replace tabs with spaces) 2015-04-13 16:19:55 +02:00
Sebastien Bourdeauducq 369086a178 soc: simplify integrated memory parameters 2015-04-02 00:09:38 +08:00
Florent Kermarrec ba8b24df57 sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy 2015-03-25 16:57:38 +01:00
Florent Kermarrec 30c2521eb0 sdram: pass sdram_controller_settings to SDRAMSoC 2015-03-21 23:12:18 +01:00
Florent Kermarrec 70469e1f37 sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit) 2015-03-21 21:32:39 +01:00
Florent Kermarrec c55199deb9 misoclib/soc: add _integrated_ to cpu options to avoid confusion 2015-03-21 20:51:37 +01:00
Florent Kermarrec 1c0e306176 targets/kc705: rename sdram_module to sdram_modules to reflect that we have 8 modules sharing the same characteristics 2015-03-21 18:07:10 +01:00
Florent Kermarrec 52924ee1f2 sdram: define MT46V32M16/MT8JTF12864 and use it on pipistrello/kc705 2015-03-21 17:25:36 +01:00
Florent Kermarrec 6e4b7c6cfd sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings 
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
 2015-03-21 12:55:39 +01:00
Florent Kermarrec 9f2e5cd7b6 targets/kc705: add external reset 2015-03-19 15:58:04 +01:00
Florent Kermarrec 28d04ec300 soc: rename with_sdram option to with_main_ram (with_sdram was confusing) 2015-03-14 00:49:19 +01:00
Florent Kermarrec 95fa753149 liteeth: add phy autodetect function (phy can still be instanciated directly) 2015-03-06 10:10:34 +01:00
Florent Kermarrec 2b9397ff5b targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True) 2015-03-06 07:56:45 +01:00
Florent Kermarrec 0716dadaf2 targets: keep the SPI flash core even if with_rom is enabled, so that flash booting in the BIOS still works 2015-03-03 10:39:31 +01:00
Florent Kermarrec 473997df26 cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases) 2015-03-02 16:52:17 +01:00
Florent Kermarrec de698c51e4 sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner) 2015-03-02 11:29:43 +01:00
Florent Kermarrec 6107b7844a test implementation on all targets and fix issues 2015-02-28 12:04:51 +01:00
Florent Kermarrec 69e869893d remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
Florent Kermarrec 2c51adcd68 misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00
Florent Kermarrec 5e2e9338d2 bios: we can now use -Ot with_rom True on targets to force bios implementation in integrated rom (can speed up debug we don't want to reflash SPI or NOR flash) 2015-02-27 17:22:44 +01:00
Florent Kermarrec b031c5edae targets: fix MiniSoC 2015-02-27 17:12:37 +01:00
Florent Kermarrec 367db268ad reserve csr_map 0-->16 for gensoc internal csrs 2015-02-27 14:18:13 +01:00
Sebastien Bourdeauducq a3909bb5e2 Merge branch 'master' of https://github.com/m-labs/misoc 2015-02-26 21:28:12 -07:00
Yann Sionneau 8364fe6674 target/kc705: allow access to pll_sys signal before BUFG 2015-02-26 15:56:10 -07:00
Florent Kermarrec 5e8a0c496d gensoc: add mem_map and mem_decoder to avoid duplications 2015-02-26 20:12:27 +01:00
Florent Kermarrec 00862a383c liteeth: fix import (from liteeth --> from misoclib.liteeth) 2015-02-26 09:48:37 +01:00
Florent Kermarrec 73ab271f9a targets/kc705: fix csr address conflict on eth 2015-02-18 10:45:18 -07:00
Florent Kermarrec 0a38b8c74a add LiteX external core and remove ethmac 2015-02-18 10:43:44 -07:00
Yann Sionneau edb1622668 spiflash: BB write support 2014-11-27 23:10:39 +08:00
Yann Sionneau cf92821fcf Refactor directory hierarchy of sdram phys and controllers 2014-11-27 22:09:10 +08:00
Sebastien Bourdeauducq 33530e0921 ethmac: style/renaming 2014-11-20 18:01:48 -08:00
Sebastien Bourdeauducq 7eaa5f7372 targets/kc705: avoid ddrphy/ethphy address conflict 2014-11-20 17:11:57 -08:00
Florent Kermarec 603c2641bb new Ethernet MAC 2014-11-20 16:47:22 -08:00
Florent Kermarrec c0c17030fd spi_flash: simplify usage by removing cmd, cmd_width, addr_width parameters 2014-09-04 15:23:39 +08:00
Sebastien Bourdeauducq 0eeb0ad9eb targets/kc705: add ddrphy to CSR map 2014-09-01 16:40:10 +08:00
Sebastien Bourdeauducq 35327a427f targets/kc705: BIOS XIP 2014-08-22 17:13:10 +08:00
Sebastien Bourdeauducq 41c8c172b5 targets/kc705: integrate DDR3 2014-08-08 21:58:41 +08:00
Sebastien Bourdeauducq fb48b89bac platforms/kc705: generate clocks for SDRAM 2014-08-06 23:53:26 +08:00
Sebastien Bourdeauducq 37968e649b targets/kc705: use PLL for clocking 2014-08-03 21:42:39 +08:00
Sebastien Bourdeauducq f7a7137127 targets: add basic KC705 2014-08-03 15:48:30 +08:00