12 Commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	e92d00f767	move software into misoc	2015-09-28 15:30:19 +08:00
Sebastien Bourdeauducq	27b2383607	sdram working on PPro	2015-09-26 21:51:22 +08:00
Sebastien Bourdeauducq	67133f3542	replace flen with len	2015-09-26 18:50:11 +08:00
Sebastien Bourdeauducq	da425d1bcb	add stream, fix CPUs and more imports. simple target boots on ppro.	2015-09-26 16:44:21 +08:00
Sebastien Bourdeauducq	75ef2f9004	fix most imports	2015-09-25 18:43:20 +08:00
Sebastien Bourdeauducq	f69674e89c	interconnect: add bus/bank components from Migen	2015-09-24 20:48:18 +08:00
Sebastien Bourdeauducq	ecdc4101b4	lasmicon: enable refresh at all times	2015-09-24 16:01:08 +08:00
Sebastien Bourdeauducq	9b08b037e4	break down sdram, improve consistency of core names	2015-09-24 15:59:55 +08:00
Sebastien Bourdeauducq	0f410e45f1	cores directory	2015-09-24 09:05:10 +08:00
Sebastien Bourdeauducq	83509163df	reorganization WIP: flatten core structure (SDRAM still needs to be done)	2015-09-24 00:18:27 +08:00
Sebastien Bourdeauducq	82236d9b40	migen.fhdl.std -> migen	2015-09-23 00:36:47 +08:00
Sebastien Bourdeauducq	bd74d39338	misoclib -> misoc	2015-09-23 00:35:02 +08:00