Sebastien Bourdeauducq
|
e97edd7253
|
genlib/fifo: disable retiming on Gray counter outputs
|
2013-04-25 14:57:07 +02:00 |
|
Sebastien Bourdeauducq
|
156ef43ace
|
genlib/cdc: add NoRetiming
|
2013-04-25 14:56:45 +02:00 |
|
Sebastien Bourdeauducq
|
b862b070d6
|
fhdl/verilog: recursive Special lowering
|
2013-04-25 14:56:26 +02:00 |
|
Sebastien Bourdeauducq
|
67c3119249
|
genlib/fifo: add asynchronous FIFO
|
2013-04-25 13:30:37 +02:00 |
|
Sebastien Bourdeauducq
|
fee228a09f
|
fhdl/specials/memory: do not write address register for async reads
|
2013-04-25 13:30:05 +02:00 |
|
Sebastien Bourdeauducq
|
6c08cd67aa
|
graycounter: expose binary output
|
2013-04-25 13:11:15 +02:00 |
|
Sebastien Bourdeauducq
|
0f9df2d732
|
genlib: add Gray counter
|
2013-04-24 19:13:36 +02:00 |
Florent Kermarrec
|
f599fe4ade
|
Support for resetless clock domains
|
2013-04-23 11:54:05 +02:00 |
|
Sebastien Bourdeauducq
|
ceb0a99d83
|
Change license to 2-clause BSD
|
2013-04-15 23:55:30 +02:00 |
|
Sebastien Bourdeauducq
|
8e11fcf1d0
|
bus/csr/SRAM: fix Module conversion errors
|
2013-04-14 13:55:04 +02:00 |
|
Sebastien Bourdeauducq
|
ea63389823
|
fhdl: support len() on all values
|
2013-04-14 13:50:26 +02:00 |
|
Sebastien Bourdeauducq
|
75d33a0c05
|
fhdl/verilog/_printinit: initialize undriven Special inputs (bug reported by Florent Kermarrec)
|
2013-04-11 18:55:49 +02:00 |
|
Sebastien Bourdeauducq
|
72ef4b9683
|
ioo+pytholite: use new Module API
|
2013-04-10 23:42:46 +02:00 |
|
Sebastien Bourdeauducq
|
4c9018ea17
|
fhdl/visit: add TransformModule
|
2013-04-10 23:42:14 +02:00 |
|
Sebastien Bourdeauducq
|
746acdacd1
|
ioo: move to genlib
|
2013-04-10 22:28:53 +02:00 |
|
Sebastien Bourdeauducq
|
1cc4c8ee9f
|
uio: remove Trampoline (Python 3.3 provides generator delegation instead)
|
2013-04-10 22:15:28 +02:00 |
|
Sebastien Bourdeauducq
|
6ce856290a
|
flow: match record fields by position
|
2013-04-10 21:33:56 +02:00 |
|
Sebastien Bourdeauducq
|
df1ed32765
|
genlib/record/connect: add match_by_position
|
2013-04-10 21:33:45 +02:00 |
|
Sebastien Bourdeauducq
|
692794a21f
|
flow: use Module and new Record APIs
|
2013-04-10 19:12:42 +02:00 |
|
Sebastien Bourdeauducq
|
20bdd424c8
|
flow: adapt to new Record API
|
2013-04-01 22:15:23 +02:00 |
|
Sebastien Bourdeauducq
|
29b468529f
|
bus: replace simple bus module with new bidirectional Record
|
2013-04-01 21:54:21 +02:00 |
|
Sebastien Bourdeauducq
|
6a3c413717
|
New bidirectional-capable Record API
|
2013-04-01 21:53:33 +02:00 |
|
Sebastien Bourdeauducq
|
c4f4143591
|
New CSR API
|
2013-03-30 17:28:41 +01:00 |
|
Sebastien Bourdeauducq
|
633e5e6747
|
fhdl/module/finalize: pass additional args to do_finalize
|
2013-03-30 11:29:46 +01:00 |
|
Sebastien Bourdeauducq
|
574becc1fc
|
fhdl/specials: clean up clock domain handling
|
2013-03-26 11:58:34 +01:00 |
|
Sebastien Bourdeauducq
|
77a0f0a3bb
|
actorlib/structuring/Cast: support inversion
|
2013-03-25 15:54:09 +01:00 |
|
Sebastien Bourdeauducq
|
c4c4765a4e
|
bank/csrgen/BankArray: retain name information
|
2013-03-25 14:44:15 +01:00 |
|
Sebastien Bourdeauducq
|
53edc3557e
|
bank/description/Register: add get_size
|
2013-03-25 14:43:44 +01:00 |
|
Sebastien Bourdeauducq
|
3da98ea04d
|
genlib/record: use getattr instead of __dict__
|
2013-03-24 00:51:01 +01:00 |
|
Sebastien Bourdeauducq
|
1897b74f97
|
genlib/record: add eq
|
2013-03-24 00:50:33 +01:00 |
|
Sebastien Bourdeauducq
|
9d7c679b8c
|
genlib/fifo: simple synchronous FIFO
|
2013-03-22 18:18:38 +01:00 |
|
Sebastien Bourdeauducq
|
ca431fc7c2
|
fhdl/module: support clock domain remapping of submodules
|
2013-03-22 18:17:54 +01:00 |
|
Sebastien Bourdeauducq
|
a94bf3b2c5
|
genlib/cdc/MultiReg: output clock domain defaults to sys
|
2013-03-21 10:40:02 +01:00 |
|
Sebastien Bourdeauducq
|
b38818eb17
|
examples/sim/fir: convert to new API
|
2013-03-19 11:46:27 +01:00 |
|
Sebastien Bourdeauducq
|
17f2b17654
|
fhdl/verilog: optionally disable clock domain creation
|
2013-03-18 18:45:19 +01:00 |
|
Sebastien Bourdeauducq
|
af4eb02551
|
examples/basic/arrays: demonstrate lowering of Array in Instance expression
|
2013-03-18 18:37:23 +01:00 |
|
Sebastien Bourdeauducq
|
7a06e9457c
|
Lowering of Special expressions + support ClockSignal/ResetSignal
|
2013-03-18 18:36:50 +01:00 |
|
Sebastien Bourdeauducq
|
dc55289323
|
fhdl/tools/_ArrayLowerer: complete support for arrays as targets
|
2013-03-18 14:38:01 +01:00 |
|
Sebastien Bourdeauducq
|
e95d2f4779
|
fhdl/tools/value_bits_sign: support not
|
2013-03-18 09:52:43 +01:00 |
|
Sebastien Bourdeauducq
|
b6fe3ace05
|
fhdl/structure: style fix
|
2013-03-17 15:33:38 +01:00 |
|
Sébastien Bourdeauducq
|
2a4cc3875c
|
Merge pull request #6 from larsclausen/master
Minor improvements
|
2013-03-17 07:33:14 -07:00 |
|
Sebastien Bourdeauducq
|
2f522bdd9f
|
genlib/cdc/MultiReg: implement rename_clock_domain + get_clock_domains
|
2013-03-15 19:50:24 +01:00 |
|
Sebastien Bourdeauducq
|
e2d156ef64
|
genlib/cdc/MultiReg: remove idomain
|
2013-03-15 19:49:24 +01:00 |
|
Sebastien Bourdeauducq
|
7b49fd9386
|
fhdl/specials: fix rename_clock_domain declarations
|
2013-03-15 19:47:01 +01:00 |
|
Sebastien Bourdeauducq
|
51bec340ab
|
sim: remove PureSimulable (superseded by Module)
|
2013-03-15 19:41:30 +01:00 |
|
Sebastien Bourdeauducq
|
dd0f3311cd
|
structure: remove Fragment.call_sim
|
2013-03-15 19:15:48 +01:00 |
|
Sebastien Bourdeauducq
|
9b9bd77d00
|
sim: compatibility with new ClockDomain API
|
2013-03-15 19:15:28 +01:00 |
|
Sebastien Bourdeauducq
|
208e039bbb
|
Local clock domain example
|
2013-03-15 18:18:32 +01:00 |
|
Sebastien Bourdeauducq
|
bd8bbd9305
|
Make ClockDomains part of fragments
|
2013-03-15 18:17:33 +01:00 |
|
Sebastien Bourdeauducq
|
5adab17efa
|
flow/actor/filter_endpoints: deterministic order
|
2013-03-14 12:20:18 +01:00 |