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Author SHA1 Message Date
Florent Kermarrec
fe4eaf5860 build/lattice/icestorm/add_period_constraint: improve 
- store period in ns.
- pass clocks to_build_pre_pack and do the convertion to MHz there.
- improve error message.
 2019-12-31 10:30:09 +01:00
Florent Kermarrec
6b91e8827c soc/integration/builder: avoid try/except on LiteDRAM import, just check if SoC has an sdram and do the import if so 2019-12-31 09:58:26 +01:00
enjoy-digital
2157d0f332
Merge pull request #327 from zakgi/master 
moving RAM offsets outside of CSR_ETHMAC define
 2019-12-31 09:49:53 +01:00
Tim 'mithro' Ansell
f0b5c67216 Allow specifying the same clock constraint multiple times. 
(As long as the clock values actually match.)
 2019-12-30 19:25:14 +01:00
Tim 'mithro' Ansell
8b955e6f69 Allow LiteX builder to be used without LiteDRAM. 2019-12-30 19:24:26 +01:00
Tim 'mithro' Ansell
a738739acd Improve the invalid CPU type error message. 2019-12-30 16:10:57 +01:00
Florent Kermarrec
85ade2b3b3 build/xilinx/programmer: fix vivado_cmd when settings are sourced manually. 2019-12-30 10:07:08 +01:00
Giammarco Zacheo
39ae230b83 moving RAM offsets outside of CSR_ETHMAC define 2019-12-29 22:56:42 -08:00
enjoy-digital
ffa7ca8f0b
Merge pull request #321 from gsomlo/gls-rocket-aximem-wide 
cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi
 2019-12-21 21:31:04 +01:00
enjoy-digital
e754c0555a
Merge pull request #319 from DurandA/feature-integer-attributes 
Add integer attributes
 2019-12-21 21:30:09 +01:00
Gabriel Somlo
cd8feca574 cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi 
Various development boards' LiteDRAM ports may have native data
widths of either 64 (nexys4ddr), 128 (versa5g), or 256 (trellis)
bits. Add Rocket variants configured with mem_axi ports of matching
data widths, so that a point to point connection between the CPU's
memory port and LiteDRAM can be accomplished without any additional
data width conversion gateware.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-12-21 14:11:48 -05:00
enjoy-digital
40c355502b
Merge pull request #320 from gsomlo/gls-touch-up 
Misc. Rocket and CSR cleanup
 2019-12-21 19:40:21 +01:00
Gabriel Somlo
585b50b292 soc_core: csr_alignment assertions 
Enforce the condition that csr_alignment be either 32 or 64 when
requested explicitly when initializing SoCCore().

Additionally, if a CPU is specified, enforce that csr_alignment be
equal to the native CPU word size (currently either 32 or 64), and
warn the caller if an alignment value *higher* than the CPU native
word size was explicitly requested.

In conclusion, if a CPU is specified, then csr_alignment should be
assumed to equal 8*sizeof(unsigned long).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-12-21 13:00:40 -05:00
Gabriel Somlo
b6818c205e cpu/rocket: access PLIC registers via pointer dereference 
Since the PLIC is internal to Rocket, access its registers
directly via pointer dereference, rather than through the
LiteX CSR Bus accessors (which assume subregister slicing,
and are therefore inappropriate for registers NOT accessed
over the LiteX CSR Bus).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-12-21 12:59:19 -05:00
Florent Kermarrec
0e46913d52 cpu/microwatt: add initial software support 2019-12-20 23:32:21 +01:00
Arnaud Durand
94e239ff13 Add integer attributes 2019-12-19 09:03:12 +01:00
Arnaud Durand
f8c5821658 Revert "gen/fhdl/verilog: allow single element verilog inline attribute" 
This reverts commit b845755995.
 2019-12-19 08:53:44 +01:00
Florent Kermarrec
f883f0c703 cpu/microwatt: add submodule 2019-12-18 19:07:08 +01:00
Florent Kermarrec
5da0bcbd7a cpu/microwatt: set csr to 0xc0000000 (IO region) 2019-12-18 08:59:35 +01:00
Florent Kermarrec
39a8ebe70c cpu/microwatt: fix add_source/add_sources 2019-12-18 08:56:36 +01:00
Florent Kermarrec
d74a7463e0 soc/cores/pwm: remove debug print(n) 2019-12-18 08:47:56 +01:00
Florent Kermarrec
bd15f07cf7 platforms/netv2: add xc7a100t support 2019-12-17 09:47:31 +01:00
Florent Kermarrec
76e57414c3 platforms/minispartan6: add assert on available devices 2019-12-17 09:47:12 +01:00
Florent Kermarrec
bfe0bf6402 cpu/microwatt: simplify add_sources 2019-12-17 09:41:46 +01:00
Florent Kermarrec
b9edde20de cpu/microwatt: add io_regions and gcc_flags 2019-12-17 09:33:46 +01:00
Florent Kermarrec
16e7c6b634 cpu/microwatt: update copyright 2019-12-17 09:27:19 +01:00
Florent Kermarrec
3d79324fce cpu/microwatt: drive stall signal (no burst support) 2019-12-16 12:37:27 +01:00
Florent Kermarrec
da3a178bc6 soc/cores/pwm: add clock_domain support 2019-12-16 11:13:10 +01:00
Florent Kermarrec
9da28c4ea5 build/xilinx/XilinxMultiRegImpl: fix n=0 case 2019-12-16 11:12:38 +01:00
Florent Kermarrec
ec7dc2d8f4 build/xilinx/ise: cleanup/simplify pass, remove mist support (not aware of anyone using it) 2019-12-14 22:47:07 +01:00
Florent Kermarrec
1b963bb2d5 soc/cores/cpu: add initial Microwatt gateware support 
Implementation tested on arty:
cd litex/soc/cores/cpu/microwatt
git clone https://github.com/antonblanchard/microwatt
mv microwatt sources

cd litex/boards/targets
./arty --cpu-type=microwatt --no-compile-gateware
 2019-12-14 00:00:13 +01:00
Florent Kermarrec
c34255d2ab soc/cores/cpu/minerva: add self.reset to i_rst 2019-12-14 00:00:07 +01:00
enjoy-digital
8b6f9e0a2c
Merge pull request #315 from gsomlo/gls-csr-assert 
soc_core: additional CSR safety assertions
 2019-12-13 21:57:14 +01:00
Gabriel Somlo
a0dad1b071 soc_core: additional CSR safety assertions 
Since csr_data_width=64 has probably never worked properly, remove
it as one of the possible options (to be fixed and re-added later).
Add csr_data_width=16, which has been tested and does work.

Additionally, ensure csr_data_width <= csr_alignment (we should not
attempt to create (sub)registers larger than the CPU's native word
size or XLen).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-12-12 13:14:16 -05:00
Florent Kermarrec
fb6b0786b6 soc_core: remove static 16MB csr region allocation (use csr_address_width to allocate the correct size) 2019-12-12 12:41:47 +01:00
Florent Kermarrec
b1a1e5e227 soc_core: add sort of CSR regions by origin (allow csr.h/csr.csv to be ordered by origin) 2019-12-12 11:27:56 +01:00
Florent Kermarrec
061d593de3 cores/8b10b: use real Memory for 6b5b table (to improve timings on ECP5) 2019-12-09 19:25:38 +01:00
Florent Kermarrec
a0122f9863 build/xilinx/vivado: move build_script generation 2019-12-08 12:19:38 +01:00
Florent Kermarrec
18ff8f38d1 build/xilinx/vivado: cleanup/simplify 2019-12-08 12:08:17 +01:00
Florent Kermarrec
0931ccc919 build/lattice/icestorm: cleanup/simplify (and remove arachne-pnr support) 2019-12-07 22:11:17 +01:00
Florent Kermarrec
b1b920531a build/xilinx/common/platform/programmer: cleanup pass 2019-12-06 22:23:04 +01:00
Florent Kermarrec
edaa66bbed boards: add Lambdaconcept's PCIe Screamer (R02) 2019-12-06 18:20:59 +01:00
Florent Kermarrec
a8635c48a4 targets/versa_ecp5: fix compilation with diamond 2019-12-06 16:15:08 +01:00
Florent Kermarrec
30a18808ad boards/targets: keep attributes are no longer needed since automatically added when applying constraints to signals. 2019-12-06 15:58:06 +01:00
Florent Kermarrec
23c33cfa99 build: automatically add keep attribute to signals with timing constraints. 
Avoid having to specify it manually or eventually forget to do it and have a constraints that is not applied correctly.
 2019-12-06 15:41:15 +01:00
Florent Kermarrec
4c9af635d2 build/altera/quartus: allow adding period constraints on nets and add optional additional sdc/qsf commands 
Additional sdc/qsf commands can be added from the design like:
platform.sdc_additional_commands.append("create_clock ...")
platform.sdc_additional_commands.append("set_false_path ...")
 2019-12-06 15:19:07 +01:00
Florent Kermarrec
22e6f5ac1d build/lattice/trellis: nextpnr now handle LPF timing constraints and multiple clock domains, freq_constraint is no longer needed. 2019-12-06 12:57:59 +01:00
Florent Kermarrec
8fb3f9a90d build/lattice: cleanup/simplify (no functional changes) 
icestorm still need to be cleaned up
 2019-12-06 12:54:52 +01:00
Florent Kermarrec
946478a71e build/lattice: cleanup/simplify 2019-12-06 12:13:20 +01:00
Florent Kermarrec
60edca2345 build/microsemi: cleanup/simplify (no functional change) 2019-12-06 12:12:43 +01:00