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Dolu1990-patch-1

allows_clk_name_override

ci-cpus

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ci-openrisc

ctu-can-fd

dma_nax

efinix_fixes

efinix_fixes2

export_csr_c_rework

framebuffer_change

generic_toolchain

ghdl_fix

gowin_emcu_uart

hyperbus_2x

hyperbus_io_regs

hyperbus_variable_latency

hyperram_decoupling

hyperram_new

kianv

liteeth_wishbone_tx_rx_buses

master

multi-channel-pwm

naxriscv-merge

naxriscv_update

neorv32_litex_wrapper

neorv32_params

usb_ohci_phy_fix

verilog_improvements

verilog_improvements_2

vexriscv_smp_irqs

video_framebuffer_skip_first_frame

video_mod_fix

wishbone_dma_ctrl

wishbone_word_byte_addressing

zynqmp_aximaster_eth_i2c_uart

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Mono Color

• 038992e7d2 corelogic: record Sebastien Bourdeauducq 2012-01-06 11:20:44 +0100
• d7a3bed44c Signal repr Sebastien Bourdeauducq 2012-01-06 11:20:33 +0100
• 4c040810bc Merge branch 'master' of github.com:milkymist/migen Sebastien Bourdeauducq 2012-01-05 19:27:55 +0100
• b60abfaa4a Convert -> convert Sebastien Bourdeauducq 2012-01-05 19:27:45 +0100
• 9366a226bb Convert -> convert Sebastien Bourdeauducq 2012-01-05 19:27:33 +0100
• 6bd8566c48 setup.py: fix to catch all modules Alain Péteut 2011-12-26 13:41:35 +0100
• 5f53e6473a Add setup script Alain Péteut 2011-12-24 13:46:08 +0100
• 1ce4fbdb98 example: flow conversion Sebastien Bourdeauducq 2011-12-23 00:36:07 +0100
• edf90870c2 flow: sum and division actors Sebastien Bourdeauducq 2011-12-23 00:35:53 +0100
• 76db20cd9f fhdl: encapsulate replicated constants Sebastien Bourdeauducq 2011-12-23 00:35:13 +0100
• f0aac4b50f flow: actor class Sebastien Bourdeauducq 2011-12-22 19:37:16 +0100
• 566295dea3 csr: use optree Sebastien Bourdeauducq 2011-12-22 19:36:56 +0100
• ba40f58491 corelogic: operator tree Sebastien Bourdeauducq 2011-12-22 15:46:19 +0100
• 8a394f9159 verilog: comb reset Sebastien Bourdeauducq 2011-12-22 00:04:53 +0100
• 4d6be55e9f verilog: break down Convert function Sebastien Bourdeauducq 2011-12-21 23:08:50 +0100
• 26e0b817e8 verilog: ignore variable property in combinatorial block Sebastien Bourdeauducq 2011-12-21 23:00:36 +0100
• 7456195775 Consistent names Sebastien Bourdeauducq 2011-12-21 22:57:07 +0100
• 47d321cd75 README: Flow Sebastien Bourdeauducq 2011-12-20 00:07:46 +0100
• d9dc604c99 README: Core Logic, Bus, Bank Sebastien Bourdeauducq 2011-12-19 23:24:31 +0100
• 7774ace7e1 README: structure + FHDL description Sebastien Bourdeauducq 2011-12-19 22:15:10 +0100
• 3b640c45bb Use new syntax Sebastien Bourdeauducq 2011-12-18 22:02:05 +0100
• af0a03b65f examples: remove old-style declarations Sebastien Bourdeauducq 2011-12-18 21:54:39 +0100
• 94c5fba067 corelogic: fix signal exports Sebastien Bourdeauducq 2011-12-18 21:54:28 +0100
• 4f4d809a4e fhdl: better matching of assignment Sebastien Bourdeauducq 2011-12-18 21:49:48 +0100
• 107f03fd4b Remove uses of declare_signal Sebastien Bourdeauducq 2011-12-18 21:47:48 +0100
• dd42b2daff fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal Sebastien Bourdeauducq 2011-12-18 21:47:29 +0100
• 41e2430e2b fhdl: automatic signal name from assignment Sebastien Bourdeauducq 2011-12-18 21:26:51 +0100
• 6664af73d1 uart: new design using FHDL and bank (TX only, incomplete) Sebastien Bourdeauducq 2011-12-18 00:29:37 +0100
• 135a2eb868 bank: support raw registers Sebastien Bourdeauducq 2011-12-18 00:28:04 +0100
• d21e095397 fhdl: fix series of if/elif/else Sebastien Bourdeauducq 2011-12-17 20:31:42 +0100
• 1a845d4553 32-device, 8-bit CSR bus Sebastien Bourdeauducq 2011-12-17 15:54:49 +0100
• bb21f7584a 32-device, 8-bit CSR bus Sebastien Bourdeauducq 2011-12-17 15:54:42 +0100
• 1b3edd07ca norflash tb: use get_fragment Sebastien Bourdeauducq 2011-12-17 15:22:26 +0100
• 6f8a6db40a verilog: get the simulator to run the combinatorial process at the beginning Sebastien Bourdeauducq 2011-12-17 15:20:22 +0100
• 0e30d67fa3 Multiply system clock Sebastien Bourdeauducq 2011-12-17 15:00:18 +0100
• 85fbe07b94 clkfx module Sebastien Bourdeauducq 2011-12-17 15:00:11 +0100
• ec47394012 verilog: support for float parameters in instances Sebastien Bourdeauducq 2011-12-17 14:59:27 +0100
• 411e1af980 Proper reset generation Sebastien Bourdeauducq 2011-12-16 22:25:26 +0100
• ee6ca729a2 verilog: user-definable reset and clock Sebastien Bourdeauducq 2011-12-16 22:25:05 +0100
• 738b45dcbd Support the new FHDL syntax Sebastien Bourdeauducq 2011-12-16 21:30:22 +0100
• c7b9dfc203 fhdl: simpler syntax Sebastien Bourdeauducq 2011-12-16 21:30:14 +0100
• 39b7190334 Pay a bit more attention to PEP8 Sebastien Bourdeauducq 2011-12-16 16:02:55 +0100
• ca68097ef6 Pay a bit more attention to PEP8 Sebastien Bourdeauducq 2011-12-16 16:02:49 +0100
• 929cc98070 wishbone2csr: wait for WB deack Sebastien Bourdeauducq 2011-12-13 17:38:59 +0100
• b487e99bcf Initial import Sebastien Bourdeauducq 2011-12-13 17:33:12 +0100
• 22d03b4943 timeline: only trigger in rest state Sebastien Bourdeauducq 2011-12-13 15:25:46 +0100
• 6f7a35e0a3 examples: Wishbone interconnect test bench Sebastien Bourdeauducq 2011-12-13 14:10:56 +0100
• c840848dba verilog: use blocking assignment in combinatorial process Sebastien Bourdeauducq 2011-12-13 14:09:12 +0100
• 92f24b784d wishbone: decoder: fix slave cyc generation in registered mode Sebastien Bourdeauducq 2011-12-13 14:08:39 +0100
• 0ea7a9b2e6 wishbone2csr: fix double-write bug Sebastien Bourdeauducq 2011-12-13 00:25:46 +0100
• 923fc52e68 wishbone: only send ack to the active master in arbiter Sebastien Bourdeauducq 2011-12-13 00:25:25 +0100
• a72faaecdd fhdl: allow a namespace to be specified for Verilog conversion Sebastien Bourdeauducq 2011-12-13 00:24:40 +0100
• eee6980a36 fhdl: support Constant parameters for Verilog conversion Sebastien Bourdeauducq 2011-12-11 20:17:51 +0100
• dafef5d744 fhdl: fix list references (thanks Lars) Sebastien Bourdeauducq 2011-12-11 20:17:29 +0100
• 16a6029a1b bus: fix CSR interconnect data readback Sebastien Bourdeauducq 2011-12-11 20:17:12 +0100
• dad9120653 bus: 14-bit CSR addresses Sebastien Bourdeauducq 2011-12-11 20:16:50 +0100
• 7582b76406 bank: fix csrgen address decoder Sebastien Bourdeauducq 2011-12-11 20:15:30 +0100
• 05d91c7104 bus: Wishbone to CSR bridge Sebastien Bourdeauducq 2011-12-11 15:04:34 +0100
• af74a89b8a corelogic: timeline module Sebastien Bourdeauducq 2011-12-11 01:11:13 +0100
• 019ef16db4 fhdl: remove broken fragment iadd Sebastien Bourdeauducq 2011-12-11 01:10:59 +0100
• b00581616e convtools: insert reset on variables Sebastien Bourdeauducq 2011-12-11 01:10:37 +0100
• d3127fd5d8 autofragment: remove debug Sebastien Bourdeauducq 2011-12-10 20:48:23 +0100
• 44f44b8a05 fhdl: autofragment Sebastien Bourdeauducq 2011-12-10 20:47:21 +0100
• 4b15a84505 fhdl: fix += for empty fragment Sebastien Bourdeauducq 2011-12-10 20:47:06 +0100
• a49ecc4331 fhdl: pad support in fragments Sebastien Bourdeauducq 2011-12-10 20:25:24 +0100
• 4d1a960308 wishbone: decoder + shared bus interconnect Sebastien Bourdeauducq 2011-12-09 13:11:52 +0100
• fa63cc1ec8 fhdl: replication support Sebastien Bourdeauducq 2011-12-09 13:11:34 +0100
• 5c7131dc86 wishbone: arbiter Sebastien Bourdeauducq 2011-12-08 23:21:25 +0100
• c1041b9a5f simplebus: export GetSigName function Sebastien Bourdeauducq 2011-12-08 23:06:04 +0100
• b2bc5ad4f4 corelogic: multimux module Sebastien Bourdeauducq 2011-12-08 23:04:34 +0100
• b0c5b74c22 verilog: handle default in case statements Sebastien Bourdeauducq 2011-12-08 23:04:20 +0100
• 512655c108 fhdl: improve automatic signal naming Sebastien Bourdeauducq 2011-12-08 21:28:20 +0100
• 5034af3038 Corelogic conversion example Sebastien Bourdeauducq 2011-12-08 21:25:05 +0100
• 62f70a54f0 corelogic: MC divider module Sebastien Bourdeauducq 2011-12-08 21:19:40 +0100
• 84eb964adc fhdl: support negation operator Sebastien Bourdeauducq 2011-12-08 21:15:44 +0100
• bf021efa2b verilog: fix unary operator conversion Sebastien Bourdeauducq 2011-12-08 21:15:24 +0100
• 78f18ad593 corelogic: round-robin module Sebastien Bourdeauducq 2011-12-08 21:15:02 +0100
• 7c99e51b90 Named buses Sebastien Bourdeauducq 2011-12-08 19:16:08 +0100
• 5720a51dad wishbone: add missing SEL Sebastien Bourdeauducq 2011-12-08 19:09:32 +0100
• ed05ec5f6a instances: signal override Sebastien Bourdeauducq 2011-12-08 18:56:14 +0100
• c43f3da534 Wishbone declarations Sebastien Bourdeauducq 2011-12-08 18:47:41 +0100
• a6b86168ce Simple bus base class Sebastien Bourdeauducq 2011-12-08 18:47:32 +0100
• 1b637cea61 Instance support Sebastien Bourdeauducq 2011-12-08 16:35:32 +0100
• fab02f84cb fhdl: fix implicit slice index Sebastien Bourdeauducq 2011-12-07 22:21:30 +0100
• 82f77180d5 fhdl: cleanup value bv Sebastien Bourdeauducq 2011-12-07 22:21:10 +0100
• 0e8d894a35 Variable conversion Sebastien Bourdeauducq 2011-12-05 22:00:06 +0100
• 4340680704 Cleanup Sebastien Bourdeauducq 2011-12-05 19:25:32 +0100
• ec51f09c98 Case support + register bank generator Sebastien Bourdeauducq 2011-12-05 17:43:56 +0100
• 458cfc8623 CSR bus definitions Sebastien Bourdeauducq 2011-12-05 00:16:44 +0100
• 5acf2e169f Examples folder Sebastien Bourdeauducq 2011-12-04 23:39:48 +0100
• e099f4d52f Reset insertion Sebastien Bourdeauducq 2011-12-04 22:41:50 +0100
• cd8544c758 Verilog generator Sebastien Bourdeauducq 2011-12-04 22:26:32 +0100
• 499b95a519 Initial import, FHDL basic structure, divider example Sebastien Bourdeauducq 2011-12-04 16:44:38 +0100