15d79ef330
fpu implement fclass and args for sub, fma, max, fcmp, fsgnj
2021-01-20 12:01:08 +01:00
11349a71fa
fpu FpuPlugin now implement all instructions.
...
Remains the FPuCore to implement cmd.arg and floating point corner cases
2021-01-19 17:57:41 +01:00
9f18045329
fpu add sstatus.fs
2021-01-19 16:06:16 +01:00
a7d148d0ff
fpu add vex csr
2021-01-19 15:53:11 +01:00
f826a2ce51
fpu completion interface added + refractoring
2021-01-19 15:13:13 +01:00
8c4fae8bf2
fpu add min/sgnj/fmv
2021-01-19 13:27:42 +01:00
d7220031d4
fpu vex i2f works
2021-01-18 17:18:01 +01:00
d4b877d415
fpu vex cmp/fle works
2021-01-18 15:09:30 +01:00
6cb498cdb2
fpu merge load/commit
2021-01-18 13:09:08 +01:00
a9d8c0a19f
fpu wip
2021-01-18 11:38:26 +01:00
3cda7c1f1b
fpu wip
2021-01-15 14:03:37 +01:00
04499c0b76
FPU sqrt functional
2021-01-14 18:33:24 +01:00
85dd5dbf8e
fpu div functional, sqrt wip
2021-01-14 15:56:56 +01:00
8761d0d9ee
FpuCore can add/mul/fma/store/load
2021-01-13 18:28:26 +01:00
6e0be6e18c
Cfu add state index and cfu index
2021-01-11 13:44:04 +01:00
930bdf9dda
DataCache increase syncPendingMax to 32 and use a sync queue instead of async one
2021-01-04 10:59:21 +01:00
780ad01ac0
Add AES-instruction support
2020-12-21 11:52:55 +01:00
c59499ec03
typo
2020-12-11 14:13:33 +01:00
eaff52b264
Add comments to the AesPlugin
2020-12-11 13:51:10 +01:00
6da09967f8
Add comments to the AesPlugin
2020-12-11 13:46:55 +01:00
9a6931a54c
CfuPlugin improve writeback buffering
2020-12-03 16:21:52 +01:00
45ff78d068
VexRiscvSmpClusterGen.dBusCmdMasterPipe option added
2020-12-01 13:51:10 +01:00
832218dbec
DBusCachedPlugin increase pendingMax to 64 to hide memory latency when saving a full context
2020-11-16 12:38:29 +01:00
ba523c627a
Fix Csr ReadWrite interration with DBusCachedPlugin execute halt
2020-11-16 12:37:48 +01:00
c1b0869c21
AesPlugin is now little endian
2020-11-12 15:07:27 +01:00
1b2a2ebaca
DBusCachedPlugin miss decoded aquire fix
2020-11-12 15:07:07 +01:00
05e725174c
AesPlugin added, work with dropbear encryption, seem ok for decryption (barmetal)
2020-11-02 17:14:52 +01:00
9abe19317d
RegFilePlugin.x0Init do less assumption on other plugin behaviour
2020-11-02 17:01:17 +01:00
576e21d75d
Do not allow jtag ebreak outside machine mode
2020-10-28 12:58:24 +01:00
abebeaea1f
Fix CsrPlugin privilege crossing
2020-10-28 12:57:20 +01:00
fe342c347c
CfuBusParameter has now a few default values
2020-10-23 11:06:24 +02:00
4ece59385d
DataCache split redo / refilling execute stage halt
2020-10-19 18:12:20 +02:00
e58daee088
SpinalHDL++
2020-10-16 11:25:25 +02:00
ec55187033
improve LightShifterPlugin arbitration halt timings
2020-10-09 11:37:48 +02:00
bbaa0520c0
Fix UserInterruptPlugin interrupt enable
2020-10-09 10:45:23 +02:00
8bd1785233
Merge pull request #141 from betrusted-io/dev-asid
...
Dev asid
2020-10-04 15:20:02 +02:00
72f85ef6c0
Merge remote-tracking branch 'origin/dev' into dev-asid
2020-10-04 19:53:29 +08:00
b7e7faebad
sbt update
2020-10-04 09:57:34 +02:00
65e6f6054b
Add ASID field to SATP
...
ASID field is missing from the SATP which causes compatibility
issues with Xous.
While this patch resolves the Xous issue, it has not been tested
on Linux.
2020-10-04 15:34:58 +08:00
3f5e771a5c
dbus mmu access improvement
2020-09-17 22:06:29 +02:00
de820daf74
add earlyBranch option to Smp config
2020-09-13 18:33:06 +02:00
49488d19af
pipeline data cache unaligned access check
2020-09-07 12:01:11 +02:00
4c3cad97d3
fix CfuPlugin generation
2020-09-04 10:36:12 +02:00
7dcaa0c390
VexRiscvSmpCluster now avoid useless decoder for plic/clint
2020-08-13 11:26:11 +02:00
69d5ba239a
Smp config now initialise regfile using logic
2020-07-28 16:15:17 +02:00
cc423cbe49
Litex cluster add DMA sel feature
2020-07-21 19:42:27 +02:00
15bda15bc9
Litex cluster can now set cache layout
2020-07-21 19:35:56 +02:00
9f62f37538
improve LitexCluster area for single core configuration
2020-07-21 15:45:02 +02:00
da666ade49
Add VexRiscvLitexSmpClusterCmdGen
2020-07-21 15:07:32 +02:00
fe5401f835
BmbGenerators refractoring (bus -> ctrl)
2020-07-16 13:04:25 +02:00
Dolu1990
bunnie