5b8febb977
Revert "Revert "Merge branch 'master' into dev""
...
This reverts commit c01c256757
2020-01-29 22:37:09 +01:00
c01c256757
Revert "Merge branch 'master' into dev"
...
This reverts commit b5374433a5f01da9c73b
2020-01-29 15:20:13 +01:00
b5374433a5
Merge branch 'master' into dev
2020-01-29 12:50:41 +01:00
052c8dd602
Fix inWfi naming, fix regressions
2019-12-20 00:21:55 +01:00
67028cdb48
Add Mul16Plugin to regression tests
...
Fix missing MulSimplePlugin in regressions tests
2019-10-21 12:53:53 +02:00
49944643d2
Add regression for data cache without writeback stage, seem to pass tests, including linux ones
2019-09-23 15:20:51 +02:00
e8236dfebe
Add MulSimplePlugin regressions
2019-09-21 12:49:46 +02:00
1257b056dc
Revert "test only dynamic_target for intensive test"
...
This reverts commit 635ef51f82
2019-06-16 18:24:59 +02:00
635ef51f82
test only dynamic_target for intensive test
2019-06-16 17:43:07 +02:00
60c9c094a7
Merge remote-tracking branch 'origin/rework_jump_flush' into dev
2019-06-15 18:09:38 +02:00
a3a0c402bc
Remove broken freertos test and add zephyr instead
2019-06-15 10:46:10 +02:00
617f4742cd
Fix dynamic branch prediction correction on misspredicted fetch which are done on a 32 bits instruction crossing two words in configs which have at least 2 cycle latency fetch
2019-06-14 08:13:22 +02:00
c8ab99cd0b
Cleaning and remove BlockQ regression
2019-06-12 00:00:38 +02:00
afbf0ea777
Fix regression makefile
2019-06-11 01:05:49 +02:00
066ddc23e6
Add regression concurrent os executions flag to avoid running debug plugin tests
2019-06-11 00:22:38 +02:00
0e95154869
individual regression : more env control
2019-06-10 21:01:41 +02:00
357681a5c6
csrPlugin add pipelinedInterrupt, set by default
2019-06-08 22:22:16 +02:00
0df4ec45ad
Merge remote-tracking branch 'origin/master' into dev
...
# Conflicts:
# build.sbt
2019-06-05 00:35:41 +02:00
49b4b61a1a
Update Bmb bridges
2019-05-20 14:14:42 +02:00
abb7bd99ab
Merge pull request #75 from SpinalHDL/dev
...
Merge dev (SpinalHDL 1.3.4)
2019-05-10 17:28:09 +02:00
db307075cf
Merge branch 'AHB' into dev
...
# Conflicts:
# src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
# src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
2019-05-07 17:21:52 +02:00
d27fa4766d
DBusCachedPlugin add earlyWaysHits in regressions
2019-05-06 00:05:40 +02:00
d12decde80
Remove test which had issues with the testbench ref checks because of getting passed delayed
2019-05-05 22:46:46 +02:00
5f18705358
Add DBusCachedPlugin.relaxedMemoryTranslationRegister option
2019-05-05 21:19:48 +02:00
d64589cc48
Add configs without memory/writeback stages in regressions
...
Add rfReadInExecute configs in regressions
Fix ShiftPluginLight and DBusSimplePlugin for configs with rfReadInExecute stage configs
2019-04-25 17:36:13 +02:00
266bdccc2e
update Riscv software model lrsc implementation
2019-04-23 21:55:54 +02:00
4078f84e8f
Dhrystone regression now also run coremark
2019-04-23 21:55:54 +02:00
c6dbaa52f6
Longer linux regression timeout for very slow configs
2019-04-21 22:16:42 +02:00
14efe6ffda
Riscv software model now implement interrupt priority accordingly to 496c59d064 (diff-a38d447c5232bd448697af4c6c8adb1a) changes
2019-04-21 20:01:39 +02:00
d7ca153c8b
remove interrupt assertion
2019-04-21 19:45:24 +02:00
0e10c460c3
Update Zephyr tests, the mem_pool_threadsafe one was bugy by the past, and now it is just too long
2019-04-21 17:58:42 +02:00
4cbb93cfc8
Look like zephyr mem_pool_threadsafe is a broken test
2019-04-21 17:48:08 +02:00
1c86bf7514
Increase liveness trigger to allow large instruction cache flush
2019-04-21 15:25:39 +02:00
963805ad48
Bring freertos back in tests
...
Better travis test range
2019-04-21 12:50:28 +02:00
edde3e3011
Add zephyr tests
2019-04-21 02:56:44 +02:00
3b0f2e9551
better travis timings
...
travis job naming
reduce verilator cache size
Fix dcache test timeout
travis cleaning
travis wip
verilator wip
fix java 10 compilation
Travis wip
travis rework
2019-04-20 14:56:56 +02:00
b49076ecab
add missing coremark patch
2019-04-19 19:41:05 +02:00
728a5ff20f
Fix coremark binaries (no csr)
2019-04-19 18:28:46 +02:00
e47b76fa67
#60 Added automated linux regression in travis
...
Fix DBusCached plugin access sharing for the MMU deadlock when exception is in the decode stage
Fix IBusSimplePlugin issues with used with non regular configs + MMU
Bring back the LinuxGen config into a light one
2019-04-19 17:35:48 +02:00
6f04c02cd2
TestInduvidualFeatures now use the linux config + MMU
2019-04-14 23:06:04 +02:00
61d25e931e
#60 Add sim error message on RVC instruction without RVC capabilities
2019-04-13 10:44:06 +02:00
5d1ec604b2
Make regression sim great again
2019-04-13 10:41:15 +02:00
9ac1d3d59e
riscv software model without RVC now trap on RVC instruction before pcWrite + 2
2019-04-13 10:40:53 +02:00
d5723968da
Merge remote-tracking branch 'origin/master' into linux
...
# Conflicts:
# src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
# src/test/cpp/regression/main.cpp
2019-04-12 16:26:08 +02:00
8421328ee1
restore freertos tests
2019-04-12 16:09:20 +02:00
ece1e73547
Default linux config is now without RVC
...
Remove all linux usless CSR from the config
Remove verilator instruction fetch check
2019-04-11 01:18:15 +02:00
926b74a203
shorter coremark
2019-04-10 15:41:58 +02:00
189cadfbb3
Add coremark
2019-04-10 15:41:38 +02:00
d7f6c18c0a
Fix DebugPlugin -> force machine mode, force uncached memory load
2019-04-10 00:35:15 +02:00
9b6b65b8b4
Fix icache test when dynamic target branch prediction is enabled
2019-04-09 19:37:18 +02:00
Charles Papon