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VexRiscv
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295 Commits

Author SHA1 Message Date
Charles Papon 534a4c3494 mmu working for instruction and data bus (both tested) 2017-05-03 18:42:54 +02:00
Charles Papon 2ed33106d6 MMU pass simple regression ! 2017-04-29 19:58:17 +02:00
Charles Papon 010ba568f0 MMU implemented 
Datacached using MMU implemented
It compile, but nothing is tested
 2017-04-28 16:41:23 +02:00
Charles Papon ba2ca77114 Two stage datacache now pass dhrystone benchmark without error 2017-04-23 23:15:38 +02:00
Charles Papon 9040326273 WIP two stage DCache, nearly passed the dhrystone benchmark 2017-04-23 18:31:16 +02:00
Charles Papon 024e14ae58 Smaller and faster single stage instruction cache 
Add fast two stage instruction cache
Remove useless address == 0 checks in the HazardPlugin
 2017-04-13 18:27:03 +02:00
Charles Papon c83a157c64 IBusCachedPlugin with twoStage config is now compatible with syncronous regfile 2017-04-09 11:59:09 +02:00
Charles Papon e3b9e671ec IBusCachedPlugin add two stage cache option for better FMax and better scaling 2017-04-08 17:42:13 +02:00
Charles Papon efb27390a7 Better IntAluPlugin 
Better SrcPlugin
Better DBusCachedPlugin
 2017-04-06 01:28:52 +02:00
Charles Papon 179e7f7b4c IBusCachedPlugin add asyncTagMemory option 2017-04-05 14:25:11 +02:00
Charles Papon 2b24cbc8e1 Add pessimistic harzard options 
Add separated add/sum option in srcPlugin
 2017-04-04 00:25:39 +02:00
Charles Papon 8ff05bd2a8 Much better decoder using Quine-Mc Cluskey 2017-04-02 21:05:25 +02:00
Charles Papon a9f7177181 Data cache pass dhrystone benchmark. 
Data cache todo -> bus error handling
 2017-04-01 17:06:59 +02:00
Charles Papon 2f384364d8 Data cache WIP 
refractoring
 2017-03-31 15:20:51 +02:00
Charles Papon 19fe998a52 Instruction cache is now able to catch bus errors 2017-03-30 17:34:24 +02:00
Charles Papon 95585b4d9a Add instruction cache plugin (tested) 2017-03-30 10:03:53 +02:00
Charles Papon 32d32845bd Add tests for iRsp, dRsp access faults 2017-03-28 20:25:58 +02:00
Charles Papon 62a55c4cf4 Add IRsp/dRsp ready + error capabilities to stall the bus and to generate access error exceptions 2017-03-28 01:24:29 +02:00
Charles Papon eecc1e6b18 Add MachineCsr.mbadaddr logics 2017-03-27 18:35:27 +02:00
Charles Papon 91c52f4e46 Decoder now catch illegal instructions 2017-03-26 18:02:48 +02:00
Charles Papon c5520656e5 Now able to catch missaligned instruction/data addresses 
Modify arbitration with an flushAll + isFlushed
 2017-03-26 17:20:07 +02:00
Charles Papon 4000191966 FreeRTOS tested 
removeIt no more colapse bubbles
 2017-03-25 16:44:42 +01:00
Charles Papon 9bbf3ee3e7 MachineCsr fix csr set/clear with zero 
MachineCsr pass external/timer interrupts test
 2017-03-24 17:40:37 +01:00
Charles Papon 72d65841d2 MachineCsr pass simple interrupt and exception tests 2017-03-23 23:12:44 +01:00
Charles Papon 94770f8e0b Add MachineCsr (untested) 2017-03-22 18:29:34 +01:00
Charles Papon e9d3977737 Add Arbitration.flushIt 
Add ExceptionService
Add unremovableStage
Add MachineCsr (untested)
 2017-03-21 18:40:50 +01:00
Charles Papon c49373f3d1 Fix missing JAL, JALR encoding 2017-03-21 10:29:09 +01:00
Charles Papon 787682d4f6 Add comments 
Some refractoring
 2017-03-20 14:49:49 +01:00
Charles Papon ecf853f491 Add Static/Dynamic branch prediction 2017-03-20 12:37:20 +01:00
Charles Papon d569242124 Add Static branch prediction in decode stage 2017-03-19 23:27:35 +01:00
Charles Papon 88dee6d2bc Reduce area with reg[0] optimisation 2017-03-18 19:32:54 +01:00
Charles Papon fc1bb7249a Add trace option to regresion 2017-03-18 14:06:42 +01:00
Charles Papon 5e9da0f27a Add self checked dhrystone test 2017-03-18 12:32:14 +01:00
Charles Papon 31db6511dc Fix performance of removed instruction which halt were halting the pipeline 2017-03-18 10:51:55 +01:00
Charles Papon 20ca348707 Fix dCmd sent while the execute stage is removed 
Pass dhrystone benchmark without error !
 2017-03-17 21:26:42 +01:00
Charles Papon 7517ac797d Add MUL/DIV/REM support with plugins (pass Riscv-Tests) 2017-03-17 11:45:01 +01:00
Charles Papon bf5bebda08 PcManager now drive PC asyncronously (use 1 cycle less in jump) 
Fix bypass logic when read/write r0
Disable REGFILE_WRITE_VALID in decod stage when r0 is written
 2017-03-15 21:10:44 +01:00
Charles Papon c6610ea454 Fix halt arbitrations 2017-03-15 17:14:58 +01:00
Charles Papon 11797fbb6e Add sim performance print 2017-03-14 23:25:04 +01:00
Charles Papon 70d910e7d7 Load/Store pass Riscv-Tests 2017-03-14 23:00:24 +01:00
Charles Papon 7065ed5d93 All base instruction pass Riscv-Test (load/store not tested) 2017-03-14 20:13:35 +01:00
Charles Papon ad6964f0bb Classify tests 
Riscv-test integration wip
 2017-03-14 00:42:48 +01:00
Charles Papon df99a0d963 Better decoding 2017-03-13 18:30:37 +01:00
Charles Papon e36c90af03 Add decoder bench 2017-03-13 16:17:57 +01:00
Charles Papon 9fc82c9736 Pass verilator simple literal, add, jump 2017-03-12 20:12:40 +01:00