Dolu1990
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2f57b46edf
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Merge pull request #23 from tomverbeure/typos
BarrielShifter -> BarrelShifter
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2018-06-03 12:29:56 +02:00 |
Tom Verbeure
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e9bbbb3965
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BarrielShifter -> BarrelShifter
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2018-06-03 07:40:11 +00:00 |
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Dolu1990
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4a433e16f1
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Merge pull request #21 from tomverbeure/typos
Typos...
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2018-05-28 20:24:52 +02:00 |
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Tom Verbeure
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0335543309
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More Unrolls
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2018-05-28 07:20:26 +00:00 |
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Tom Verbeure
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1613191779
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Unrool -> Unroll
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2018-05-28 07:18:13 +00:00 |
Dolu1990
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1752b5f184
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Give name to inter stages registers
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2018-05-27 23:39:49 +02:00 |
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Dolu1990
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c4f33b30e2
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Update SynthesisBench murax
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2018-05-24 14:03:28 +02:00 |
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Dolu1990
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6c47a3b2a3
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update key
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2018-05-17 19:07:58 +02:00 |
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Dolu1990
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e63e57981e
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travis test upload
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2018-05-17 19:04:35 +02:00 |
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Dolu1990
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042962c1ae
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Fix travis
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2018-05-17 18:56:31 +02:00 |
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Dolu1990
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938ed6abf6
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Add bintraykey
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2018-05-17 18:52:21 +02:00 |
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Dolu1990
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81790c32b8
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Add travis
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2018-05-17 18:43:52 +02:00 |
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Dolu1990
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4e7152ae5a
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IcestormFlow add ultraplus support
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2018-05-14 20:18:53 +02:00 |
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Dolu1990
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558af595a1
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Add ice40 synthesis results
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2018-04-26 13:14:37 +02:00 |
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Dolu1990
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bdcf3f6234
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Add HexTools and add a Briey main which load the ram
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2018-04-26 10:27:39 +02:00 |
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Dolu1990
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cfc324aa0f
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Allow csr mtvec to not have reset values
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2018-04-24 23:33:48 +02:00 |
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Dolu1990
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a9cbc48eb2
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PcManagerPlugin is can now handle an external reset vector signal
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2018-04-24 23:11:11 +02:00 |
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Dolu1990
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c7d852c497
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Merge remote-tracking branch 'origin/Wishbone'
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2018-04-22 12:15:25 +02:00 |
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Dolu1990
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978eb9b6b2
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DBusCachedPlugin add CSR info
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2018-04-22 11:46:01 +02:00 |
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Dolu1990
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74f2a4194a
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Add ExternalInterruptArrayPlugin
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2018-04-20 17:56:21 +02:00 |
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Dolu1990
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6598e82920
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wishbone => word address, not byte address
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2018-04-19 11:22:06 +02:00 |
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Dolu1990
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455607b6b4
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Fix dBus IO access
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2018-04-18 14:11:59 +02:00 |
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Dolu1990
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6e59ddcc73
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Cached wishbone demo is passing regression tests
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2018-04-18 13:51:33 +02:00 |
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Dolu1990
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b37fc3fcc8
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Add VexRiscv Wishbone demo for sim (generation ok)
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2018-04-18 12:54:20 +02:00 |
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Dolu1990
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a66efcb35b
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Add wishbone support for i$ / d$ (not tested)
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2018-04-17 23:56:44 +02:00 |
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Dolu1990
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bd4d1eeb01
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Update briey soc diagram
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2018-03-24 13:49:50 +01:00 |
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Dolu1990
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925f6ae811
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Update README.md
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2018-03-22 15:25:40 +01:00 |
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Dolu1990
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cd4ffc2f3f
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Update README.md
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2018-03-22 15:24:56 +01:00 |
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Dolu1990
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7da85303dd
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Update README.md
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2018-03-22 14:40:08 +01:00 |
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Dolu1990
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64022557bf
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Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl
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2018-03-15 18:56:25 +01:00 |
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Dolu1990
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63c1b738ff
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Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings
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2018-03-14 00:56:23 +01:00 |
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Dolu1990
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d9b7426cde
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undo InOutWrapper from Murax
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2018-03-14 00:47:23 +01:00 |
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Dolu1990
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2f8f4d5444
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SpinalHDL 1.1.5
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2018-03-13 15:45:56 +01:00 |
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Dolu1990
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7ea3e24183
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update readme perf
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2018-03-10 18:37:38 +01:00 |
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Dolu1990
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91031f8d75
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DivPlugin is now based MulDivIterativePlugin (Smaller)
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2018-03-10 13:31:35 +01:00 |
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Dolu1990
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f133e69fed
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fix readme toc
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2018-03-10 13:04:48 +01:00 |
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Dolu1990
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578e54376a
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Add MulDivIterativePlugin in readme
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2018-03-10 12:57:42 +01:00 |
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Dolu1990
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e437a1d44e
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Add division support in the MulDivInterativePlugin
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2018-03-09 22:41:47 +01:00 |
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Dolu1990
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36438bd306
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iterative mul improvments
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2018-03-09 20:00:50 +01:00 |
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Dolu1990
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674ab2c594
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experimental iterative mul/div combo
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2018-03-09 19:07:26 +01:00 |
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Dolu1990
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5228a53293
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MuraxSim improve simulation Speed
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2018-03-06 12:20:39 +01:00 |
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Dolu1990
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9b2cd7b234
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MuraxSim add switch
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2018-03-06 12:17:15 +01:00 |
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Dolu1990
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53970dd284
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SpinalHDL 1.1.4
Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
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2018-03-05 14:34:59 +01:00 |
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Dolu1990
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b159ccf8ed
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Update README.md
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2018-02-27 22:43:53 +01:00 |
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Dolu1990
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ccad64def5
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Pipeline CSR isWrite
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2018-02-26 10:19:33 +01:00 |
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Dolu1990
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2b6185b063
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Decoding logic : Add primes duplication removal
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2018-02-25 08:57:31 +01:00 |
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Dolu1990
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2b6f43cef8
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Fix Murax memory mapping range
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2018-02-25 08:57:31 +01:00 |
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Dolu1990
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5260ad5c35
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Decoding lib cleaning
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2018-02-25 08:57:31 +01:00 |
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Dolu1990
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137b1ee32c
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Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values
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2018-02-22 22:36:13 +01:00 |
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Dolu1990
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d957934949
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Fix ICache exception priority over miss reload
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2018-02-19 22:44:46 +01:00 |