4de0aac469
Merge branch 'formal'
2017-11-24 14:03:25 +01:00
b7f4f09814
Update verilator makefiles to support the last SpinalHDL changes (process merges)
2017-11-21 23:56:46 +01:00
9b9bbaa4ad
Add missing full config for the iBus
2017-11-21 00:09:02 +01:00
ce6fd6d0aa
Add VexRiscvAxi4 demo
2017-11-20 23:57:37 +01:00
7c19288648
Update Synthesis bench
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Update some synthesis results
2017-11-17 20:10:46 +01:00
635417aec2
Merge pull request #9 from kaofishy/master
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Minor fixes to Murax.scala
2017-11-16 21:16:53 +01:00
290dbc106e
Fixes GPIO width mismatch
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Adds explicit type to apbDecoder.slave to suppress IDE errors
2017-11-16 15:02:13 -05:00
9f9ec823b8
SpinalHDL 0.11.2
2017-11-15 17:57:08 +01:00
6c3fed3505
SpinalHDL 0.11.1
2017-11-15 16:44:42 +01:00
be3d301eaf
Merge remote-tracking branch 'origin/spinalhdl_reworkDev'
2017-11-12 13:08:05 +01:00
838c13d68b
spinal.core.internals literals import
2017-11-10 13:14:30 +01:00
3060296b94
unsetRegIfNoAssignement -> allowUnsetRegToAvoidLatch
2017-11-10 11:33:04 +01:00
c3a7f4e58c
CSR unsetRegIfNoAssignement fix
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BranchPlugin doesn't emit the prediction cache when the STATIC setup is used
2017-11-10 00:59:31 +01:00
d6777ae8ec
usetRegIfNoAssign upgrade
2017-11-09 20:10:56 +01:00
a72c7fd0d1
Clean Murax toplevel by extracting integrated Area into dedicated components located in MuraxUtiles.scala
2017-11-07 22:19:33 +01:00
714d44d248
Add fixed bug into the FormalPlugin comments
2017-11-07 13:54:07 +01:00
0cf278b04f
Update README.md
2017-11-07 00:12:58 +01:00
200a73bea0
Fix FormalPlugin to pass liveness again.
2017-11-06 23:04:33 +01:00
8098a03a9b
with no bus stall, pass all tests except uniqueness
2017-11-06 20:26:45 +01:00
e2a432eb5e
add HaltOnExceptionPlugin
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wip
2017-11-05 20:13:27 +01:00
276f7895e7
Add FormalPlugin
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Add FormalSimple CPU configuration
2017-11-04 00:55:32 +01:00
ba42f71813
pass VexRiscv regressions
2017-10-30 14:29:25 +01:00
173336af33
Update README.md
2017-10-20 14:44:31 +02:00
9d75349d7a
Merge pull request #6 from plex1/master
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updated main.cpp
2017-10-18 00:17:49 +02:00
008a5b7309
updated main.cpp
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added missing using namespace std
2017-10-17 22:09:08 +00:00
228623a309
Update pinsec picture
2017-10-16 12:06:24 +02:00
6f0c792cb8
Add brieySoc.png image
2017-10-16 12:02:40 +02:00
2bf7ca24f2
Add VexRiscvAvalonWithIntegratedJtag
2017-10-16 11:52:17 +02:00
8857bcd7f6
Add documentation about resets
2017-10-16 11:31:03 +02:00
aa859aae6b
Update framework.h
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Add missing using namespace std;
2017-10-05 10:08:09 +02:00
0327c5ec3a
Update README.md
2017-08-31 10:09:11 +02:00
09ba7c28da
Change some xx.input(REGFILE_WRITE_DATA) for xx.output(REGFILE_WRITE_DATA)
2017-08-27 15:21:44 +02:00
8168c9bf3a
Update simd_add makefile
2017-08-27 14:49:36 +02:00
a8191b6092
Fix sbt version to 0.13.7
2017-08-17 03:39:52 +02:00
d543325294
script about gcc prebuild version
2017-08-17 02:46:12 +02:00
3db3795e0a
Update sbteclipse-plugin
2017-08-17 02:04:25 +02:00
7811d90f99
update gcc path
2017-08-14 12:16:40 +02:00
8fbd777794
Update readme with GCC changes from the VexRiscvSocSoftware repo
2017-08-14 11:40:33 +02:00
85fa3776d3
Readme fix typo
2017-08-11 13:49:27 +02:00
2c6889e688
Murax mainBus now handle unmapped memory access allowing the debug to access unmapped area without locking the CPU
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Murax add dhrystone config
2017-08-10 22:48:00 +02:00
6072e9157e
Update VexRiscv area/Fmax
2017-08-10 22:13:19 +02:00
aa477b2b1c
DebugPlugin now prevent the CPU catching exception when debug instruction are pushed
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Fix DataCache locking when loading mem read rsp transaction has the flag set
Briey : Now the debug module reset the whole AXI system instead of only the CPU
Now in debug, you can access unmapped memory without crashing the CPU
2017-08-10 20:56:54 +02:00
37f2674d5b
Add commands to genreate the SIMD_ADD cpu
2017-08-08 18:44:32 +02:00
1653548140
Better readme about custum instruction testing
2017-08-08 18:36:23 +02:00
54b06e6438
Add SIMD_ADD regression and config (show case)
2017-08-08 18:19:02 +02:00
3307d6c3b5
Briey move CPU and UART generics from to toplevel to the toplevel configuration object
2017-08-06 15:42:37 +02:00
665df18ee9
Add version information about verilator on readme
2017-08-05 19:14:08 +02:00
671aa5050e
Move CPU and UART configs into the murax configuration object (in place of toplevel hardcoding)
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Add MuraxConfig.fast
2017-08-04 14:55:54 +02:00
9f65a21f3e
Readme add information about the Murax with a demo program in ROM
2017-08-04 00:17:29 +02:00
c033b32fc9
scripts/murax remove jtag pullup which apparently break the functionality
2017-08-03 23:59:48 +02:00
Dolu1990
Dolu1990
Tony Kao
Ubuntu