Dolu1990
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49488d19af
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pipeline data cache unaligned access check
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2020-09-07 12:01:11 +02:00 |
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Dolu1990
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4c3cad97d3
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fix CfuPlugin generation
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2020-09-04 10:36:12 +02:00 |
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Dolu1990
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7dcaa0c390
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VexRiscvSmpCluster now avoid useless decoder for plic/clint
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2020-08-13 11:26:11 +02:00 |
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Dolu1990
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69d5ba239a
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Smp config now initialise regfile using logic
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2020-07-28 16:15:17 +02:00 |
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Dolu1990
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cc423cbe49
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Litex cluster add DMA sel feature
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2020-07-21 19:42:27 +02:00 |
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Dolu1990
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15bda15bc9
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Litex cluster can now set cache layout
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2020-07-21 19:35:56 +02:00 |
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Dolu1990
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9f62f37538
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improve LitexCluster area for single core configuration
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2020-07-21 15:45:02 +02:00 |
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Dolu1990
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da666ade49
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Add VexRiscvLitexSmpClusterCmdGen
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2020-07-21 15:07:32 +02:00 |
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Dolu1990
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fe5401f835
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BmbGenerators refractoring (bus -> ctrl)
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2020-07-16 13:04:25 +02:00 |
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Dolu1990
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da73317912
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Cleanup BmbGenerators
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2020-07-15 20:51:46 +02:00 |
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Dolu1990
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5f0aec7570
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BmbInterconnectGenerator refractoring
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2020-07-15 17:03:05 +02:00 |
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Dolu1990
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4f5ba6b044
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Merge branch 'bmbRework' into dev
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2020-07-10 13:06:20 +02:00 |
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Dolu1990
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f6931784a5
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Merge branch 'smp' into dev
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2020-07-10 13:00:50 +02:00 |
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Dolu1990
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d0a572de98
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Add openroad config
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2020-07-08 01:37:10 +02:00 |
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Dolu1990
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32f778613f
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DBusCachedPlugin now support asyncTagMemory
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2020-07-08 01:36:58 +02:00 |
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Dolu1990
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60ee7e2b4c
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Better VexRiscvSmpCluster config
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2020-07-08 01:36:40 +02:00 |
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Dolu1990
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51070d0e69
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Fix MmuPlugin when used in multi stage config
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2020-07-05 13:17:39 +02:00 |
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Dolu1990
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06584518da
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Remove CsrPlugin redoInterface combinatorial depedency from execut_isStuck
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2020-07-05 13:17:07 +02:00 |
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Dolu1990
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a404078117
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Few fixes
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2020-07-05 13:16:39 +02:00 |
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Dolu1990
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c51e25f8c4
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Litex SoC add coherent DMA master
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2020-07-05 13:15:44 +02:00 |
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Dolu1990
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32539dfe6d
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Got VexRiscvSmpLitexCluster refractoring to work
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2020-06-30 22:29:33 +02:00 |
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Dolu1990
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0da94ac66f
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Bring back smp cluster parameters
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2020-06-29 15:49:01 +02:00 |
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Dolu1990
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062509deee
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Update Bmb brides and comment out SmpCluster for now
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2020-06-29 11:44:10 +02:00 |
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Dolu1990
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c12f9a378d
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Fix inv regression
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2020-06-20 13:18:46 +02:00 |
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Dolu1990
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f0f2cf61da
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D$ inv/ack are now fragment, which ease serialisation of wider invalidations
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2020-06-19 15:57:56 +02:00 |
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Dolu1990
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c18bc12cb2
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Fix DebugPlugin.fromBmb
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2020-06-19 15:57:21 +02:00 |
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Dolu1990
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490c1f6b02
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cleanup of old todo
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2020-06-19 15:56:45 +02:00 |
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Dolu1990
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b0cd88c462
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SmpCluster now with proper jtag and plic
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2020-06-12 16:18:41 +02:00 |
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Dolu1990
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2e8a059c77
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Fix travis verilator
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2020-06-07 11:33:24 +02:00 |
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Dolu1990
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cb5597818d
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Fix d$ generation crash
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2020-06-07 11:29:07 +02:00 |
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Dolu1990
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1f9fce6388
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Fix d$ uncached writes exception handeling
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2020-06-06 22:12:37 +02:00 |
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Dolu1990
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760d2f74d0
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Update litex cluster to implement utime
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2020-06-05 13:31:24 +02:00 |
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Dolu1990
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d6455817e7
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smp cluster now have 2w*4KB of d$ , no more rdtime emulation
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2020-06-05 10:43:03 +02:00 |
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Dolu1990
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71760ea372
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CsrPlugin now support utime csr to avoid emulation
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2020-06-05 10:43:03 +02:00 |
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Dolu1990
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3dafe8708b
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Cfu update
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2020-06-05 10:43:03 +02:00 |
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Dolu1990
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0668046407
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More smp cluster profiling
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2020-06-05 10:40:51 +02:00 |
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Dolu1990
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97c2dc270c
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Fix typo
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2020-06-04 10:11:30 +02:00 |
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Dolu1990
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89c13bedbd
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Fix litex smp cluster sim
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2020-06-03 16:31:54 +02:00 |
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Dolu1990
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73f88e47cb
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Fix BmbToLitexDram coherency
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2020-06-03 16:31:54 +02:00 |
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Dolu1990
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db50f04653
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Add litexMpCluster
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2020-06-03 16:31:54 +02:00 |
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Dolu1990
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08189ee907
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DebugPlugin now support Bmb
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2020-06-02 19:13:55 +02:00 |
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Dolu1990
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5e5c730959
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Add LitexSmpDevCluster with per cpu dedicated litedram ports
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2020-05-29 10:56:55 +02:00 |
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Dolu1990
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bc4a2c3747
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Fix SmpCluster jtag
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2020-05-27 14:19:37 +02:00 |
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Dolu1990
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18cce053a3
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Improve SingleInstructionLimiterPlugin to also include fetch stages
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2020-05-27 14:19:17 +02:00 |
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Dolu1990
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a64fd9cf3b
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Add CsrPlugin external hartid
d$ rsp/sync now decrement pendings by signal amount
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2020-05-20 13:49:10 +02:00 |
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Dolu1990
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380afa3130
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SpinalHDL 1.4.2
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2020-05-20 13:45:52 +02:00 |
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Dolu1990
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c3540bc6e0
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SpinalHDL 1.4.2
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2020-05-20 10:37:52 +02:00 |
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Dolu1990
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cf60989ae1
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Litex smp cluster now blackboxify d$ data ram
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2020-05-14 00:05:54 +02:00 |
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Dolu1990
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42fef8bbcd
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Smp cluster now use i$ reduceBankWidth
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2020-05-12 23:59:38 +02:00 |
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Dolu1990
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685c914227
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Add i$ reduceBankWidth to take advantage of multi way by remaping the data location to reduce on chip ram data width
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2020-05-12 23:59:38 +02:00 |