John McMaster
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93d8a38664
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README.md: add missing newline
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
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2018-07-11 11:28:59 -07:00 |
Dolu1990
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32fe1dcbd4
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Add google cloud VM regressions scripts
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2018-07-07 21:47:09 +02:00 |
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Dolu1990
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ce54fd78e4
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wip
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2018-07-07 11:40:02 +02:00 |
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Dolu1990
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3ea4f28354
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wip
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2018-07-07 11:39:42 +02:00 |
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Dolu1990
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9c1a8ea219
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Fix EPC
Fix Freertos binaries
wip
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2018-07-03 23:17:32 +02:00 |
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Dolu1990
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ffe5fa23f0
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wip
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2018-06-25 09:36:07 +02:00 |
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Dolu1990
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d73aa9ce00
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rework csr exception/interrupt handeling wip
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2018-06-24 00:14:55 +02:00 |
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Dolu1990
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dd47db9ad0
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wip
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2018-06-20 12:35:12 +02:00 |
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Dolu1990
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8886f7e6d4
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test wip
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2018-06-19 16:15:42 +02:00 |
Dolu1990
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6c673b0749
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Merge pull request #27 from tomverbeure/typos
README language
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2018-06-19 11:18:28 +02:00 |
Tom Verbeure
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43ab18fb83
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Unrool -> Unroll
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2018-06-19 02:02:43 -07:00 |
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Tom Verbeure
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68cc141401
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Language
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2018-06-19 01:53:31 -07:00 |
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Tom Verbeure
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dda9fe76e2
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an -> a
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2018-06-19 01:41:24 -07:00 |
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Tom Verbeure
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8d22f74c83
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Language
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2018-06-19 01:39:37 -07:00 |
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Tom Verbeure
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4e9e8b3e55
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Language
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2018-06-18 17:19:37 -07:00 |
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Tom Verbeure
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5c9c43aa00
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Language
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2018-06-18 17:09:29 -07:00 |
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Dolu1990
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1090111a6f
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TestIndividual is now fully random
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2018-06-15 13:00:59 +02:00 |
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Dolu1990
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b2cd8c5314
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Fix exception pipelining
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2018-06-15 13:00:26 +02:00 |
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Dolu1990
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83864710a3
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Fix IBusCached single cycle interaction with mmu bus
Add random test configs
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2018-06-09 08:40:19 +02:00 |
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Dolu1990
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d10bcbfbbb
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Update README.md
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2018-06-08 19:06:30 +02:00 |
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Dolu1990
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505a92916a
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Update README.md
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2018-06-08 18:00:22 +02:00 |
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Dolu1990
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4e73d4ff7d
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Update README.md
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2018-06-08 12:43:33 +02:00 |
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Dolu1990
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d9a049aa72
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Update README.md
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2018-06-08 12:31:55 +02:00 |
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Dolu1990
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08a1212fca
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Add DBus simple/cached regressions
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2018-06-07 02:31:18 +02:00 |
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Dolu1990
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6bc5431fcd
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Add iBusCached regressions
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2018-06-07 00:57:26 +02:00 |
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Dolu1990
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5e7dd02bf7
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Fix relaxedPc/DYNAMIC_TARGET interaction
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2018-06-06 18:30:30 +02:00 |
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Dolu1990
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dc968020c4
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Fix relaxedBusCmdValid pendingCmd overflow
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2018-06-06 15:20:37 +02:00 |
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Dolu1990
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7768f065e4
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Add many cpu configs on regressions tests (some config are broken)
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2018-06-06 02:23:07 +02:00 |
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Dolu1990
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8729530a8d
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Fix Dynamicfetch/!rvc config
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2018-06-05 02:33:18 +02:00 |
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Dolu1990
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930563291c
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Allow RVC/dynamic_target/fetch bus latency > 1 all together
Fix freeretos rvc regressions
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2018-06-05 02:21:05 +02:00 |
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Dolu1990
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702db29edd
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Fix dynamic prediction RVC allignement
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2018-06-04 20:03:08 +02:00 |
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Dolu1990
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fc835f370e
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Fix DynamicPrediction with RVC missprediction between ret instruction and first instruction of the next function
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2018-06-04 19:45:15 +02:00 |
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Dolu1990
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cee3ad8147
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Merge pull request #24 from tomverbeure/typos
Fix some missing Barriel -> barriel fixes
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2018-06-04 11:09:05 +02:00 |
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Tom Verbeure
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52f1cdbca7
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Fix some missing Barriel -> barriel fixes
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2018-06-03 21:46:40 -07:00 |
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Dolu1990
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9f0387350b
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Add Freertos RVC binaries regression
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2018-06-03 17:10:58 +02:00 |
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Dolu1990
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2f57b46edf
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Merge pull request #23 from tomverbeure/typos
BarrielShifter -> BarrelShifter
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2018-06-03 12:29:56 +02:00 |
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Tom Verbeure
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e9bbbb3965
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BarrielShifter -> BarrelShifter
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2018-06-03 07:40:11 +00:00 |
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Dolu1990
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7375855e58
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DYNAMIC_PREDICTION used with RVC pass tests (1 cycle fetch)
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2018-06-03 00:50:18 +02:00 |
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Dolu1990
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98b68093f4
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dynamic_prediction + RVC => instruction fetch stopped midair
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2018-05-28 21:28:39 +02:00 |
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Dolu1990
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d65a7703ec
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Fix travis ?
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2018-05-28 20:53:52 +02:00 |
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Dolu1990
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4a433e16f1
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Merge pull request #21 from tomverbeure/typos
Typos...
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2018-05-28 20:24:52 +02:00 |
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Dolu1990
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863ac3f34d
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dynamic prediction now use history from first aligned word of the instruction instead of the last one.
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2018-05-28 11:03:13 +02:00 |
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Dolu1990
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8a0c238bf3
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dynamic prediction ok with rvc, todo dynamic_target with rvc
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2018-05-28 10:59:22 +02:00 |
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Tom Verbeure
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0335543309
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More Unrolls
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2018-05-28 07:20:26 +00:00 |
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Tom Verbeure
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1613191779
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Unrool -> Unroll
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2018-05-28 07:18:13 +00:00 |
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Dolu1990
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7493e70265
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Merge remote-tracking branch 'origin/master' into reworkFetcher
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2018-05-28 09:02:30 +02:00 |
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Dolu1990
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5943ee727e
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Fill travis, DhrystoneBench is now a Unit test
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2018-05-28 09:02:01 +02:00 |
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Dolu1990
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1752b5f184
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Give name to inter stages registers
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2018-05-27 23:39:49 +02:00 |
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Dolu1990
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5704f22739
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wip
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2018-05-27 23:33:57 +02:00 |
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Dolu1990
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346338f084
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Better HexTools
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2018-05-26 11:51:42 +02:00 |