0e2d40c37f
Merge remote-tracking branch 'origin/pipelinedInterrupt'
2019-06-09 12:29:20 +02:00
357681a5c6
csrPlugin add pipelinedInterrupt, set by default
2019-06-08 22:22:16 +02:00
0df4ec45ad
Merge remote-tracking branch 'origin/master' into dev
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# Conflicts:
# build.sbt
2019-06-05 00:35:41 +02:00
56f7c27d18
Fix WFI. Not sensitive anymore to global interrupt enables, delegation and privilege
2019-06-05 00:32:38 +02:00
64e8919e89
Update README.md
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Add litex repo
2019-05-28 11:28:07 +02:00
38a464a829
DataCache now allocate ways randomly
2019-05-25 00:28:30 +02:00
4a40184b35
Add cache Bandwidth counter, previous commit was about random instruction cache way allocation
2019-05-25 00:22:27 +02:00
94606d38e2
Add cache bandwidth counter
2019-05-25 00:21:48 +02:00
206c7ca638
Fix Bmb datacache bridge
2019-05-24 00:22:58 +02:00
f6f94ad7c1
Fix InstructionCache Bmb bridge
2019-05-22 19:03:26 +02:00
9b49638654
Allow CsrPlugin config access
2019-05-22 17:27:47 +02:00
8abc06c8f2
Add Bmb support for i$/d$
2019-05-22 17:04:36 +02:00
49b4b61a1a
Update Bmb bridges
2019-05-20 14:14:42 +02:00
f249bbc60a
Merge remote-tracking branch 'origin/tmp'
2019-05-18 20:35:28 +02:00
b40dc06b29
SpinalHDL 1.3.5
2019-05-18 19:56:03 +02:00
0301ced000
Fix dBusSimplePlugin to bmb bridge
2019-05-16 19:49:13 +02:00
4ce9d805b4
Switch to unreleased SpinalHDL
2019-05-14 00:41:14 +02:00
3753f64429
Fix Bmb compilation
2019-05-13 23:44:20 +02:00
abb7bd99ab
Merge pull request #75 from SpinalHDL/dev
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Merge dev (SpinalHDL 1.3.4)
2019-05-10 17:28:09 +02:00
8201cff7ff
SpinalHDL 1.3.4
2019-05-10 14:27:14 +02:00
db307075cf
Merge branch 'AHB' into dev
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# Conflicts:
# src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
# src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
2019-05-07 17:21:52 +02:00
01db217ab9
Add supervisor support in the ExternalInterruptArrayPlugin
2019-05-06 16:23:43 +02:00
3094f8b349
Merge remote-tracking branch 'origin/dBusCachedRelaxMmuTranslation'
2019-05-06 01:36:56 +02:00
91f6bf5139
Merge branch 'dBusCachedRelaxMmuTranslation'
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# Conflicts:
# src/test/scala/vexriscv/TestIndividualFeatures.scala
2019-05-06 01:36:11 +02:00
d27fa4766d
DBusCachedPlugin add earlyWaysHits in regressions
2019-05-06 00:05:40 +02:00
d12decde80
Remove test which had issues with the testbench ref checks because of getting passed delayed
2019-05-05 22:46:46 +02:00
8f1b980337
Revert "Add DBusCachedPlugin.relaxedMemoryTranslationRegister option"
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This reverts commit 5f18705358
2019-05-05 22:29:33 +02:00
5f18705358
Add DBusCachedPlugin.relaxedMemoryTranslationRegister option
2019-05-05 21:19:48 +02:00
c738246610
Remove the legacy pipelining from Axi4 cacheless bridges
2019-05-01 12:03:01 +02:00
7d99a70e9c
Switch to released SpinalHDL
2019-05-01 12:02:27 +02:00
02db756b21
Merge remote-tracking branch 'origin/master' into dev
2019-04-29 16:56:04 +02:00
fa13e46e87
Merge pull request #71 from xobs/mmu-2-stage
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Mmu 2 stage
2019-04-26 14:25:29 +02:00
d1e215e312
caches: work without writeBack stage
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In the case of an MMU miss, the data caches will create a retry branch port.
These currently implicitly go into the memory/writeBack stage, however
not all CPUs have this stage.
Place the retry branch port into the correct stage.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-26 18:02:43 +08:00
b2f387ccac
MmuPlugin: fix generation without writeBack stage
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If there is no writeBack stage, the elaboration step would hit a
NullPointerException when trying to insert into the writeBack stage.
Instead, pull from the most recent stage, which is where MMU access
should reside.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-26 18:01:35 +08:00
6fc5406901
Merge branch 'linux'
2019-04-25 23:20:01 +02:00
0edc781b36
Add some coremark results
2019-04-25 23:18:45 +02:00
10255f2f81
Update readme
2019-04-25 21:11:23 +02:00
d64589cc48
Add configs without memory/writeback stages in regressions
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Add rfReadInExecute configs in regressions
Fix ShiftPluginLight and DBusSimplePlugin for configs with rfReadInExecute stage configs
2019-04-25 17:36:13 +02:00
431bec84fb
Switch to SpinalHDL 1.3.3 (release)
2019-04-24 22:17:46 +02:00
017e17f9fa
Update synthesis results in the readme
2019-04-24 12:32:57 +02:00
74e5cc49f9
Add the linux config into the synthesis bench
2019-04-24 12:32:37 +02:00
a331f35724
Icestorm flow now use nextpnr
2019-04-24 12:32:24 +02:00
b654d824ad
remove DebugPlugin from linux.scala, and set static branch prediction
2019-04-23 21:55:54 +02:00
266bdccc2e
update Riscv software model lrsc implementation
2019-04-23 21:55:54 +02:00
4078f84e8f
Dhrystone regression now also run coremark
2019-04-23 21:55:54 +02:00
c6dbaa52f6
Longer linux regression timeout for very slow configs
2019-04-21 22:16:42 +02:00
633e057d11
Split machine os regression in two smaller parts
2019-04-21 20:30:58 +02:00
14efe6ffda
Riscv software model now implement interrupt priority accordingly to 496c59d064 (diff-a38d447c5232bd448697af4c6c8adb1a) changes
2019-04-21 20:01:39 +02:00
d7ca153c8b
remove interrupt assertion
2019-04-21 19:45:24 +02:00
0e10c460c3
Update Zephyr tests, the mem_pool_threadsafe one was bugy by the past, and now it is just too long
2019-04-21 17:58:42 +02:00
Charles Papon
Sean Cross