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751 commits 39 branches 2 tags 15 MiB
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282 commits

Author SHA1 Message Date
Charles Papon
617f4742cd Fix dynamic branch prediction correction on misspredicted fetch which are done on a 32 bits instruction crossing two words in configs which have at least 2 cycle latency fetch 2019-06-14 08:13:22 +02:00
Charles Papon
c8ab99cd0b Cleaning and remove BlockQ regression 2019-06-12 00:00:38 +02:00
Charles Papon
afbf0ea777 Fix regression makefile 2019-06-11 01:05:49 +02:00
Charles Papon
066ddc23e6 Add regression concurrent os executions flag to avoid running debug plugin tests 2019-06-11 00:22:38 +02:00
Charles Papon
0e95154869 individual regression : more env control 2019-06-10 21:01:41 +02:00
Charles Papon
357681a5c6 csrPlugin add pipelinedInterrupt, set by default 2019-06-08 22:22:16 +02:00
Dolu1990
abb7bd99ab
Merge pull request #75 from SpinalHDL/dev 
Merge dev (SpinalHDL 1.3.4)
 2019-05-10 17:28:09 +02:00
Charles Papon
db307075cf Merge branch 'AHB' into dev 
# Conflicts:
#	src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
#	src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
 2019-05-07 17:21:52 +02:00
Charles Papon
d27fa4766d DBusCachedPlugin add earlyWaysHits in regressions 2019-05-06 00:05:40 +02:00
Charles Papon
d12decde80 Remove test which had issues with the testbench ref checks because of getting passed delayed 2019-05-05 22:46:46 +02:00
Charles Papon
5f18705358 Add DBusCachedPlugin.relaxedMemoryTranslationRegister option 2019-05-05 21:19:48 +02:00
Charles Papon
d64589cc48 Add configs without memory/writeback stages in regressions 
Add rfReadInExecute configs in regressions
Fix ShiftPluginLight and DBusSimplePlugin for configs with rfReadInExecute stage configs
 2019-04-25 17:36:13 +02:00
Charles Papon
266bdccc2e update Riscv software model lrsc implementation 2019-04-23 21:55:54 +02:00
Charles Papon
4078f84e8f Dhrystone regression now also run coremark 2019-04-23 21:55:54 +02:00
Charles Papon
c6dbaa52f6 Longer linux regression timeout for very slow configs 2019-04-21 22:16:42 +02:00
Charles Papon
14efe6ffda Riscv software model now implement interrupt priority accordingly to 496c59d064 (diff-a38d447c5232bd448697af4c6c8adb1a) changes 2019-04-21 20:01:39 +02:00
Charles Papon
d7ca153c8b remove interrupt assertion 2019-04-21 19:45:24 +02:00
Charles Papon
0e10c460c3 Update Zephyr tests, the mem_pool_threadsafe one was bugy by the past, and now it is just too long 2019-04-21 17:58:42 +02:00
Charles Papon
4cbb93cfc8 Look like zephyr mem_pool_threadsafe is a broken test 2019-04-21 17:48:08 +02:00
Dolu1990
1c86bf7514 Increase liveness trigger to allow large instruction cache flush 2019-04-21 15:25:39 +02:00
Charles Papon
963805ad48 Bring freertos back in tests 
Better travis test range
 2019-04-21 12:50:28 +02:00
Charles Papon
edde3e3011 Add zephyr tests 2019-04-21 02:56:44 +02:00
Charles Papon
3b0f2e9551 better travis timings 
travis job naming
reduce verilator cache size
Fix dcache test timeout
travis cleaning
travis wip
verilator wip
fix java 10 compilation
Travis wip
travis rework
 2019-04-20 14:56:56 +02:00
Charles Papon
b49076ecab add missing coremark patch 2019-04-19 19:41:05 +02:00
Charles Papon
728a5ff20f Fix coremark binaries (no csr) 2019-04-19 18:28:46 +02:00
Charles Papon
e47b76fa67 #60 Added automated linux regression in travis 
Fix DBusCached plugin access sharing for the MMU deadlock when exception is in the decode stage
Fix IBusSimplePlugin issues with used with non regular configs + MMU
Bring back the LinuxGen config into a light one
 2019-04-19 17:35:48 +02:00
Charles Papon
6f04c02cd2 TestInduvidualFeatures now use the linux config + MMU 2019-04-14 23:06:04 +02:00
Charles Papon
61d25e931e #60 Add sim error message on RVC instruction without RVC capabilities 2019-04-13 10:44:06 +02:00
Charles Papon
5d1ec604b2 Make regression sim great again 2019-04-13 10:41:15 +02:00
Charles Papon
9ac1d3d59e riscv software model without RVC now trap on RVC instruction before pcWrite + 2 2019-04-13 10:40:53 +02:00
Charles Papon
d5723968da Merge remote-tracking branch 'origin/master' into linux 
# Conflicts:
#	src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
#	src/test/cpp/regression/main.cpp
 2019-04-12 16:26:08 +02:00
Charles Papon
8421328ee1 restore freertos tests 2019-04-12 16:09:20 +02:00
Charles Papon
ece1e73547 Default linux config is now without RVC 
Remove all linux usless CSR from the config
Remove verilator instruction fetch check
 2019-04-11 01:18:15 +02:00
Charles Papon
926b74a203 shorter coremark 2019-04-10 15:41:58 +02:00
Charles Papon
189cadfbb3 Add coremark 2019-04-10 15:41:38 +02:00
Charles Papon
d7f6c18c0a Fix DebugPlugin -> force machine mode, force uncached memory load 2019-04-10 00:35:15 +02:00
Charles Papon
9b6b65b8b4 Fix icache test when dynamic target branch prediction is enabled 2019-04-09 19:37:18 +02:00
Charles Papon
a6dc530441 Added lrsc/amo tests 2019-04-09 19:27:42 +02:00
Charles Papon
fd42e7701e Add hardware AMO, require AMO=yes in sim and withAmo=true in linux.scala 2019-04-09 01:22:32 +02:00
Charles Papon
21cb8615fd Clean and fix things to get all the non-linux configs and machine only configs working 2019-04-08 16:06:05 +02:00
Charles Papon
ddf0f06834 Add more delegation tests 
Reduce dcache test duration
 2019-04-05 22:56:12 +02:00
Charles Papon
aeb418a99e Add dcache tests 2019-04-05 20:03:22 +02:00
Charles Papon
8459d423b8 add icache flush test 2019-04-05 18:11:33 +02:00
Charles Papon
8e6010fd71 Got the debug plugin working with the linux config (had to disable CSR ebreak) 2019-04-05 00:25:27 +02:00
Charles Papon
4f0a02594c Change LR/SC to reserve the whole memory 
Fix MPP access from other plugins
Got all the common configuration to compile and pass regression excepted the debugger one
First synthesis results
 2019-04-04 20:34:35 +02:00
Charles Papon
8be40e637b #60 Got the new data cache design passing all tests and running linux 2019-04-02 23:44:53 +02:00
Charles Papon
fd4da77084 #60 Got the new instruction cache design passing the standard regressions 2019-04-02 00:26:53 +02:00
Charles Papon
bc0af02c97 #60 Got instruction cache running linux :D 2019-04-01 11:59:04 +02:00
Charles Papon
e74a5a71eb Better simulation console integration 2019-04-01 10:31:55 +02:00
Charles Papon
369a3d0f5f #60 Sync everything, added much comment on the top of Linux.scala to help reproduce 2019-03-31 23:43:56 +02:00