Hardware/VexRiscv
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480 commits 39 branches 2 tags 15 MiB
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314 commits

Author SHA1 Message Date
Dolu1990
68f1ff3222 Add CsrPlugin ebreak support 2018-10-10 19:23:04 +02:00
Dolu1990
0662cc2797 Add GenMicro experiment to reduce ice40 area usage. 
IBusSimplePlugin now require cmdFork parameters to be set (no default)
 2018-10-03 22:08:57 +02:00
Dolu1990
48bff80653 rework fetchPc to optionaly share the pcReg with the stage(1) 
IBusSimplePlugin now implement cmdForkPersistence option
 2018-10-03 16:24:10 +02:00
Dolu1990
c61f17aea3 Fetcher/IBusSimplePlugin wip 2018-10-03 01:02:22 +02:00
Dolu1990
0ada869b2d regression golden ref regfile is now sync with trl boot's random values 
wip
 2018-10-01 16:14:21 +02:00
Dolu1990
65a8d84d30 Introduce HAS_SIDE_EFFECT Stageable to solve sensitive instruction squeduling 
(uncached DBus TODO)
 2018-10-01 12:13:05 +02:00
Dolu1990
7770eefa3b wip 2018-09-30 12:57:08 +02:00
Dolu1990
39c6bc11d6 Pass basic regression again 2018-09-29 19:04:20 +02:00
Dolu1990
5ad7c39f47 wip 2018-09-29 12:04:58 +02:00
Dolu1990
37a1970ad6 wip 2018-09-28 16:02:33 +02:00
Dolu1990
9a3510f63d Map all supervisor registers 2018-09-27 19:03:57 +02:00
Dolu1990
acd1ca422a wip 2018-09-27 18:24:40 +02:00
Dolu1990
6dde73f97c Murax demo with XIP is now fully defined in SpinalHDL 2018-09-27 00:55:30 +02:00
Dolu1990
aff436ddcf Sync with SpinalHDL head 
Add mmu test into the dhrystone regression command
 2018-09-24 18:31:33 +02:00
Dolu1990
1e3b75ef1d xip typo 2018-09-23 22:06:21 +02:00
Dolu1990
86efb75f6a rework fetcher 2018-09-23 22:05:53 +02:00
Dolu1990
56fd73fbbc Add missing bin files 2018-09-23 19:26:11 +02:00
Dolu1990
bdc3246f5a Fix xip gitignore 2018-09-23 19:23:43 +02:00
Dolu1990
5024cc5616 Hardware breakpoint feature added 
Murax XIP debugging passed tests
 2018-09-20 13:11:20 +02:00
Dolu1990
ff1d1072a7 XIP is physicaly working on murax 2018-09-19 00:09:14 +02:00
Dolu1990
b51ac03a5e murax xip flash integration wip 2018-09-18 16:53:26 +02:00
Dolu1990
3e17461cc7 Add optional XIP to Murax 2018-09-16 11:00:56 +02:00
Dolu1990
d7cba38ec2 move to SpinalHDL 1.1.7, add more default value for plugins parameters 2018-09-11 16:08:28 +02:00
Dolu1990
791608f655 Move swing stuff into main test package 2018-08-29 14:55:25 +02:00
Dolu1990
0255f51cc5 Add unpipelined Wishbone support for uncached version 2018-08-24 16:41:34 +02:00
Dolu1990
7ed6835e97 Add C++ VexRiscv model to cross check the hardware simulation 2018-08-22 02:08:55 +02:00
Dolu1990
38af5dbdd5 riscv emulator WIP (RVC missing) 2018-08-21 01:03:51 +02:00
Dolu1990
dca1e5f438 revert RVC from murax 2018-08-17 23:12:45 +02:00
Dolu1990
8ebb3af4fc Merge remote-tracking branch 'origin/master' into reworkFetcher 
Conflicts:
	README.md
	src/main/scala/vexriscv/TestsWorkspace.scala
	src/test/scala/vexriscv/Play.scala
 2018-08-17 20:56:51 +02:00
Dolu1990
9c7e089329 Fix ExternalInterruptArrayPlugin CSR ids 2018-08-17 20:38:33 +02:00
Dolu1990
330ee14a23 final fetchRework commit ? 2018-08-17 19:13:23 +02:00
Dolu1990
91773ec7d5 Sync, Seem to pass all except dynamic_o0 which is probably a freertos test setup issue 2018-08-14 11:51:53 +02:00
Dolu1990
9c1a8ea219 Fix EPC 
Fix Freertos binaries
wip
 2018-07-03 23:17:32 +02:00
Dolu1990
ffe5fa23f0 wip 2018-06-25 09:36:07 +02:00
Dolu1990
d73aa9ce00 rework csr exception/interrupt handeling wip 2018-06-24 00:14:55 +02:00
Dolu1990
dd47db9ad0 wip 2018-06-20 12:35:12 +02:00
Dolu1990
8886f7e6d4 test wip 2018-06-19 16:15:42 +02:00
Dolu1990
1090111a6f TestIndividual is now fully random 2018-06-15 13:00:59 +02:00
Dolu1990
b2cd8c5314 Fix exception pipelining 2018-06-15 13:00:26 +02:00
Dolu1990
83864710a3 Fix IBusCached single cycle interaction with mmu bus 
Add random test configs
 2018-06-09 08:40:19 +02:00
Dolu1990
5e7dd02bf7 Fix relaxedPc/DYNAMIC_TARGET interaction 2018-06-06 18:30:30 +02:00
Dolu1990
dc968020c4 Fix relaxedBusCmdValid pendingCmd overflow 2018-06-06 15:20:37 +02:00
Dolu1990
7768f065e4 Add many cpu configs on regressions tests (some config are broken) 2018-06-06 02:23:07 +02:00
Dolu1990
8729530a8d Fix Dynamicfetch/!rvc config 2018-06-05 02:33:18 +02:00
Dolu1990
930563291c Allow RVC/dynamic_target/fetch bus latency > 1 all together 
Fix freeretos rvc regressions
 2018-06-05 02:21:05 +02:00
Dolu1990
702db29edd Fix dynamic prediction RVC allignement 2018-06-04 20:03:08 +02:00
Dolu1990
fc835f370e Fix DynamicPrediction with RVC missprediction between ret instruction and first instruction of the next function 2018-06-04 19:45:15 +02:00
Dolu1990
9f0387350b Add Freertos RVC binaries regression 2018-06-03 17:10:58 +02:00
Tom Verbeure
e9bbbb3965 BarrielShifter -> BarrelShifter 2018-06-03 07:40:11 +00:00
Dolu1990
7375855e58 DYNAMIC_PREDICTION used with RVC pass tests (1 cycle fetch) 2018-06-03 00:50:18 +02:00