Charles Papon
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087e3dda89
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Add Murax scripts
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2017-07-29 22:43:43 +02:00 |
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Charles Papon
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2736681be6
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Add Murax in the readme
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2017-07-29 22:25:28 +02:00 |
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Charles Papon
|
e8aa828744
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PcPlugin change fastPcCalculation into relaxedPcCalculation
relaxedPcCalculation relax timings on the IBusSimple address => better FMax when the CPU is integrated into a SoC
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2017-07-29 21:36:30 +02:00 |
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Charles Papon
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3b66d986a8
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Fix cpu sending instruction memory request while being halted by the DebugPlugin
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2017-07-29 18:20:22 +02:00 |
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Charles Papon
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43253f61c1
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Update Murax info
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2017-07-29 02:52:57 +02:00 |
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Charles Papon
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fa887d3830
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Add pipelining option (hit 60 Mhz)
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2017-07-29 02:52:03 +02:00 |
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Charles Papon
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3bdf020c67
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Add interrupts and timer to Murax
8KB ram is the default now
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2017-07-29 01:59:17 +02:00 |
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Charles Papon
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823ac353ff
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Add Murax SoC (very light, work on ice40)
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2017-07-28 21:25:49 +02:00 |
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Dolu1990
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1450077b70
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Add Murax SoC (wip)
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2017-07-28 14:16:30 +02:00 |
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Charles Papon
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493f7721cb
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All FreeRTOS tests are now passing
|
2017-07-28 00:07:51 +02:00 |
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Charles Papon
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800e9e79a5
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freertos regression now include O0 and O3 for rv32i and rv32im
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2017-07-27 01:23:50 +02:00 |
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Charles Papon
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6b3e2dbe7d
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Add FreeRTOS test regression (FREERTOS=yes)
Multithreaded regression
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2017-07-26 23:38:59 +02:00 |
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Charles Papon
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10d282b2ef
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Add DBusSimple early injection feature (better DMIPS)
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2017-07-26 23:36:25 +02:00 |
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Charles Papon
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6d117f5c81
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Fix DataCache bug (interaction between the victim buffer and the memory read request in execute/memory stages)
freeRTOS pass
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2017-07-23 22:58:26 +02:00 |
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Charles Papon
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9fe4e1d54d
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Package refractoring VexRiscv -> vexriscv Plugin -> plugin
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2017-07-23 13:28:17 +02:00 |
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Charles Papon
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4b5bf7d807
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Briey Area down by 10% by spliting the memory system in two (System, Debug)
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2017-07-23 01:11:33 +02:00 |
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Charles Papon
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37c338ec98
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Avalon add read response support.
Fix debug instruction injection and IBusSimplePlugin interraction
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2017-07-21 20:39:54 +02:00 |
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Charles Papon
|
54f785b1a3
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Add full avalon support (pass regression)
|
2017-07-21 17:40:45 +02:00 |
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Charles Papon
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52f5020e64
|
Rename some regression commands
Add Avalon regressions (PASS)
DebugModule read response is now 1 cycle latency
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2017-07-21 14:32:49 +02:00 |
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Charles Papon
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575a410786
|
Avalon regression (WIP)
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2017-07-20 14:20:19 +02:00 |
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Charles Papon
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570f0e1e3e
|
D$ remove the coupling between the mem.cmd.ready >> victim logic >> cpu halt by using halfPipe => Better practical FMax
|
2017-07-20 14:20:19 +02:00 |
|
Dolu1990
|
950944e040
|
typo fix
|
2017-07-19 18:36:30 +02:00 |
|
Dolu1990
|
8643086fc0
|
Add Briey area and timings into readme
|
2017-07-19 18:34:16 +02:00 |
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Dolu1990
|
02c9b0be75
|
readme add full no cache
|
2017-07-17 16:52:36 +02:00 |
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Charles Papon
|
42e546ecd9
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Add fullNoMmuNoCache config
|
2017-07-17 16:45:06 +02:00 |
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Dolu1990
|
2b03b8487d
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Add Small and productive in readme
|
2017-07-17 15:38:52 +02:00 |
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Charles Papon
|
fcec6cba86
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revert test changes
|
2017-07-17 15:26:37 +02:00 |
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Charles Papon
|
617861ee6c
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Add smallAndProductive
|
2017-07-17 15:25:56 +02:00 |
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Charles Papon
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431750cac3
|
readme update TOC
|
2017-07-17 14:22:13 +02:00 |
|
Charles Papon
|
99c3397243
|
readme, better plugin example
|
2017-07-17 14:19:28 +02:00 |
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Charles Papon
|
84bba3adf0
|
REG1/REG2 refractoring RS1/RS2
Add CustomeInstruction example
|
2017-07-17 14:02:56 +02:00 |
|
Dolu1990
|
708a8f66de
|
typo fixes
|
2017-07-17 14:01:35 +02:00 |
|
Dolu1990
|
a4ac2ca8ce
|
Fix typo
|
2017-07-16 20:41:03 +02:00 |
|
Dolu1990
|
5190ba28e0
|
readme add features
|
2017-07-16 19:06:05 +02:00 |
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Dolu1990
|
59e09ce269
|
Exclude TCL from the repo
|
2017-07-16 18:24:28 +02:00 |
|
Dolu1990
|
a38b137db2
|
readme ToC fix
|
2017-07-16 18:10:03 +02:00 |
|
Dolu1990
|
cd2fb402c1
|
readme ToC fix
|
2017-07-16 18:08:39 +02:00 |
|
Dolu1990
|
3134725aa9
|
readme ToC fix
|
2017-07-16 18:06:45 +02:00 |
|
Dolu1990
|
43ac85aaf6
|
Readme add index and demonstrator
|
2017-07-16 17:47:32 +02:00 |
|
Dolu1990
|
8635054b38
|
cleaning
|
2017-07-16 14:42:24 +02:00 |
|
Dolu1990
|
79c2972076
|
Update bench config with realistic embedded CSR
|
2017-07-16 14:34:42 +02:00 |
|
Dolu1990
|
53300c4116
|
Add area and FMax in readme
Add Synthesis bench
|
2017-07-16 13:50:19 +02:00 |
|
Dolu1990
|
37ea699c55
|
Add Synthesis bench
|
2017-07-16 03:29:50 +02:00 |
|
Charles Papon
|
6930e76042
|
Remove mepc from smallest CSR config
Better readme
|
2017-07-16 00:44:23 +02:00 |
|
Charles Papon
|
bc792a8655
|
Fix UartRx sim
|
2017-07-15 19:05:34 +02:00 |
|
Charles Papon
|
74becb6633
|
Add VexRiscvAvalon QSysify
|
2017-07-15 09:41:39 +02:00 |
|
Charles Papon
|
12d21a08e8
|
Add DebugPlugin avalon
|
2017-07-14 19:28:22 +02:00 |
|
Charles Papon
|
d3dcfcec06
|
Add toAvalon bridge to cached bus
Add VexRiscvAvalon demo
|
2017-07-14 18:04:41 +02:00 |
|
Charles Papon
|
b9cbb27b81
|
Add Briey informations
|
2017-07-09 18:02:01 +02:00 |
|
Charles Papon
|
f51f28164a
|
Fix info to flush data cache
Briey sim add VGA GUI (SDL2)
Add DE0-Nano Briey support
|
2017-07-09 01:00:46 +02:00 |