Dolu1990
|
c51e25f8c4
|
Litex SoC add coherent DMA master
|
2020-07-05 13:15:44 +02:00 |
|
Dolu1990
|
32539dfe6d
|
Got VexRiscvSmpLitexCluster refractoring to work
|
2020-06-30 22:29:33 +02:00 |
|
Dolu1990
|
0da94ac66f
|
Bring back smp cluster parameters
|
2020-06-29 15:49:01 +02:00 |
|
Dolu1990
|
062509deee
|
Update Bmb brides and comment out SmpCluster for now
|
2020-06-29 11:44:10 +02:00 |
|
Dolu1990
|
c12f9a378d
|
Fix inv regression
|
2020-06-20 13:18:46 +02:00 |
|
Dolu1990
|
f0f2cf61da
|
D$ inv/ack are now fragment, which ease serialisation of wider invalidations
|
2020-06-19 15:57:56 +02:00 |
|
Dolu1990
|
c18bc12cb2
|
Fix DebugPlugin.fromBmb
|
2020-06-19 15:57:21 +02:00 |
|
Dolu1990
|
490c1f6b02
|
cleanup of old todo
|
2020-06-19 15:56:45 +02:00 |
|
Dolu1990
|
b0cd88c462
|
SmpCluster now with proper jtag and plic
|
2020-06-12 16:18:41 +02:00 |
|
Dolu1990
|
2e8a059c77
|
Fix travis verilator
|
2020-06-07 11:33:24 +02:00 |
|
Dolu1990
|
cb5597818d
|
Fix d$ generation crash
|
2020-06-07 11:29:07 +02:00 |
|
Dolu1990
|
1f9fce6388
|
Fix d$ uncached writes exception handeling
|
2020-06-06 22:12:37 +02:00 |
|
Dolu1990
|
760d2f74d0
|
Update litex cluster to implement utime
|
2020-06-05 13:31:24 +02:00 |
|
Dolu1990
|
d6455817e7
|
smp cluster now have 2w*4KB of d$ , no more rdtime emulation
|
2020-06-05 10:43:03 +02:00 |
|
Dolu1990
|
71760ea372
|
CsrPlugin now support utime csr to avoid emulation
|
2020-06-05 10:43:03 +02:00 |
|
Dolu1990
|
3dafe8708b
|
Cfu update
|
2020-06-05 10:43:03 +02:00 |
|
Dolu1990
|
0668046407
|
More smp cluster profiling
|
2020-06-05 10:40:51 +02:00 |
|
Dolu1990
|
97c2dc270c
|
Fix typo
|
2020-06-04 10:11:30 +02:00 |
|
Dolu1990
|
89c13bedbd
|
Fix litex smp cluster sim
|
2020-06-03 16:31:54 +02:00 |
|
Dolu1990
|
73f88e47cb
|
Fix BmbToLitexDram coherency
|
2020-06-03 16:31:54 +02:00 |
|
Dolu1990
|
db50f04653
|
Add litexMpCluster
|
2020-06-03 16:31:54 +02:00 |
|
Dolu1990
|
08189ee907
|
DebugPlugin now support Bmb
|
2020-06-02 19:13:55 +02:00 |
|
Dolu1990
|
5e5c730959
|
Add LitexSmpDevCluster with per cpu dedicated litedram ports
|
2020-05-29 10:56:55 +02:00 |
|
Dolu1990
|
bc4a2c3747
|
Fix SmpCluster jtag
|
2020-05-27 14:19:37 +02:00 |
|
Dolu1990
|
18cce053a3
|
Improve SingleInstructionLimiterPlugin to also include fetch stages
|
2020-05-27 14:19:17 +02:00 |
|
Dolu1990
|
a64fd9cf3b
|
Add CsrPlugin external hartid
d$ rsp/sync now decrement pendings by signal amount
|
2020-05-20 13:49:10 +02:00 |
|
Dolu1990
|
380afa3130
|
SpinalHDL 1.4.2
|
2020-05-20 13:45:52 +02:00 |
|
Dolu1990
|
c3540bc6e0
|
SpinalHDL 1.4.2
|
2020-05-20 10:37:52 +02:00 |
|
Dolu1990
|
cf60989ae1
|
Litex smp cluster now blackboxify d$ data ram
|
2020-05-14 00:05:54 +02:00 |
|
Dolu1990
|
42fef8bbcd
|
Smp cluster now use i$ reduceBankWidth
|
2020-05-12 23:59:38 +02:00 |
|
Dolu1990
|
685c914227
|
Add i$ reduceBankWidth to take advantage of multi way by remaping the data location to reduce on chip ram data width
|
2020-05-12 23:59:38 +02:00 |
|
Dolu1990
|
0471c7ad76
|
Fix machineCsr test
|
2020-05-12 23:55:47 +02:00 |
|
Dolu1990
|
cb44a474fc
|
more smp cluster profiling
|
2020-05-12 13:25:55 +02:00 |
|
Dolu1990
|
63511b19a2
|
smp cluster add more profiling
|
2020-05-11 10:35:24 +02:00 |
|
Charles Papon
|
b592b0bff8
|
Add regression TRACE_SPORADIC, LINUX_SOC_SMP
regression golden model now properly sync dut exceptions
|
2020-05-09 17:00:13 +02:00 |
|
Dolu1990
|
0a159f06b2
|
update smp config
|
2020-05-07 22:50:36 +02:00 |
|
Dolu1990
|
0e76cf9ac8
|
i$ now support multi cycle MMU
|
2020-05-07 22:50:25 +02:00 |
|
Dolu1990
|
41ee8fd226
|
MmuPlugin now support multiple stages, D$ can now take advantage of that
|
2020-05-07 13:37:53 +02:00 |
|
Dolu1990
|
8e025aeeaa
|
more litex smp cluster pipelining
|
2020-05-07 13:18:11 +02:00 |
|
Dolu1990
|
fc0f3a2020
|
cleanup mmu interface
|
2020-05-06 18:05:20 +02:00 |
|
Dolu1990
|
6323caf265
|
MMU now allow $ to match tag against tlb pyhsical values directly
D$ retiming
D$ directTlbHit feature added for better timings
|
2020-05-06 17:09:46 +02:00 |
|
Dolu1990
|
ed4a89e4af
|
more pipelineing in Litex SMP cluster interconnect
|
2020-05-06 17:06:45 +02:00 |
|
Dolu1990
|
8043feebd5
|
More VexRiscv smp cluster probes
|
2020-05-06 17:06:17 +02:00 |
|
Dolu1990
|
09724e907b
|
play around with CSR synthesis impact on design size
|
2020-05-05 00:32:59 +02:00 |
|
Dolu1990
|
c16f2ed787
|
Add probes in SmpCluster sim
|
2020-05-04 12:54:28 +02:00 |
|
Dolu1990
|
b0f7f37ac8
|
D$ now support memDataWidth > 32
|
2020-05-04 12:54:16 +02:00 |
|
Dolu1990
|
93b386e16e
|
litex smp cluster now use OO decoder
|
2020-05-02 23:44:58 +02:00 |
|
Dolu1990
|
f0745eb0d9
|
update SMP line size to 64 bytes
|
2020-05-02 23:44:27 +02:00 |
|
Dolu1990
|
09ac23b78f
|
Fix SMP fence lock when 4 stages CPU
|
2020-05-01 12:45:16 +02:00 |
|
Dolu1990
|
f5f30615ba
|
Got litex SMP cluster to work on FPGA
|
2020-05-01 11:14:52 +02:00 |