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VexRiscv
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580 Commits

Author SHA1 Message Date
Dolu1990 c34f5413a3 Add MMU MPRIV for easier machinemode emulation #60 2019-03-25 10:30:13 +01:00
Dolu1990 9d55283b3b Machine mode emulator 2019-03-25 02:00:19 +01:00
Dolu1990 e28702eb40 Add PlicCost test 2019-03-24 12:17:39 +01:00
Dolu1990 6c0608f0dd #60 
Add LitexSoC workspace / linux loading.
Need to emulate peripherals and adapte the kernel now.
Probably also need some machine mode emulation
Software time !
 2019-03-24 10:52:56 +01:00
Dolu1990 0656a49332 Make xtval more compliant 2019-03-23 20:12:36 +01:00
Dolu1990 7159237104 Fix csrrs/csrrc for xip registers 2019-03-23 18:11:26 +01:00
Dolu1990 505bff6f45 CSR Plugin now implement interruptions as specified in the spec 2019-03-23 12:56:04 +01:00
Dolu1990 3652ede130 Add mdeleg tests 2019-03-23 11:41:10 +01:00
Dolu1990 9139b4d269 Restore all tests 2019-03-22 18:03:35 +01:00
Dolu1990 597336b491 MMU sum/mxr tested and ok, all seem finen 2019-03-22 17:11:55 +01:00
Dolu1990 f7b793b7bf Add SSTATUS.SUM/MXR feature, need testing 2019-03-22 15:49:36 +01:00
Dolu1990 e4cdc2397a MMU pass all test, need to and SUM and MXR and it's all ok 2019-03-22 14:52:49 +01:00
Dolu1990 2b458fc642 Added MMU superpage support, pass MMU tests 2019-03-22 12:23:47 +01:00
Dolu1990 af2acbd46e Got the new MMU design to pass simple tests #60 2019-03-22 01:10:17 +01:00
Dolu1990 ea56481ead Add supervisor CSR in the riscv golden model 2019-03-20 23:26:08 +01:00
Dolu1990 7cbe399f1f Fix some supervisor CSR access 2019-03-20 23:25:52 +01:00
Dolu1990 6f2e5a0eb7 goldenmodel Implement some of the supervisor CSR 2019-03-20 20:28:04 +01:00
Dolu1990 39b2803914 Fix some CsrPlugin flags issues 2019-03-20 20:27:47 +01:00
Dolu1990 6c2fe934fd Bring changes and fixies from @kgugala @daveshah1. Thanks guys ! 2019-03-20 16:27:35 +01:00
Dolu1990 130a69eeae Pass regressions machinemode with CSR config including Supervisor 2019-03-20 14:14:59 +01:00
Dolu1990 d205f88fb8 riscv golden model and RTL pass all current regressions 
add RVC into the linux config
 2019-03-20 12:17:43 +01:00
Dolu1990 3c66f7c58a goldenmodel now pass more machine mode CSR tests 2019-03-20 11:46:27 +01:00
Dolu1990 ee402ec5dc clearning 2019-03-20 01:16:39 +01:00
Dolu1990 3a38fe4130 Add mmu regresion blank project 2019-03-20 01:13:05 +01:00
Dolu1990 ccc3b63d7c Enable golden model check for all regressions 
Need to implement missing CSR of the golden model
 2019-03-20 01:12:03 +01:00
Dolu1990 8f22365959 Disable MMU in machine mode 2019-03-19 22:21:30 +01:00
Dolu1990 3fbc2f4458 Fix generation 2019-03-19 20:29:28 +01:00
Dolu1990 915db9d6c9 cleaning 2019-03-18 20:50:19 +01:00
Dolu1990 001ca45c57 Add cachless dBus IBus access right checks 2019-03-18 12:52:22 +01:00
Dolu1990 c490838202 Added MMU support into cacheless DBus IBus plugins (for testing purposes) 
Probably full of bugs, need testing
 2019-03-18 12:17:43 +01:00
Dolu1990 ffa489d211 hardware refilled MmuPlugin wip 2019-03-17 21:06:47 +01:00
Dolu1990 03663ce91a Move unreleased SpinalHDL 2019-03-15 17:35:31 +01:00
Dolu1990 2e0b63bc67 SpinalHDL 1.3.2 2019-03-10 11:12:43 +01:00
Dolu1990 bad60f39cd Fix Decoding benchmark 2019-03-10 11:12:32 +01:00
Dolu1990 434793711b fix part of #59 2019-02-26 17:26:42 +01:00
Dolu1990 b9922105f0 Fix readme demo path 2019-02-26 17:22:13 +01:00
Dolu1990 e0c8ac01d2 Add custom external interrupts 2019-02-03 15:20:34 +01:00
Dolu1990 11f55359c6 IBusCache can now avoid injectorStage in singleStage mode 2019-01-30 01:37:47 +01:00
Dolu1990 f4598fbd0a Add tightly coupled interface to the i$ 2019-01-21 23:46:18 +01:00
Dolu1990 8f1b4cc8e5 Merge branch 'master' into dev 2019-01-16 16:32:12 +01:00
Dolu1990 b5caca54cd restore all feature in TestsWorkspace 2019-01-16 15:25:50 +01:00
Dolu1990 f4f854ae4f SpinalHDL 1.3.1 2019-01-14 13:32:16 +01:00
Dolu1990 dcdfa79024 fix run-main into runMain 2019-01-03 20:07:38 +01:00
Dolu1990 414d2aba54 Merge remote-tracking branch 'origin/dev' 2018-12-30 15:54:14 +01:00
Dolu1990 927ab6d127 Merge remote-tracking branch 'origin/master' into dev 2018-12-30 15:53:25 +01:00
Dolu1990 92065a1a10 Update to SpinalHDL 1.3.0 2018-12-30 15:51:46 +01:00
Dolu1990 dd42e30c61 Merge remote-tracking branch 'origin/master' into dev 2018-12-29 14:04:07 +01:00
Dolu1990 d617bafb08 Roll back VexRiscvAvalonForSim to use caches 2018-12-25 00:15:23 +01:00
Dolu1990 1da055dc34
Merge pull request #49 from cutephoton/avalon 
Avalon: Debug Clock Domain for JTAG
 2018-12-23 16:27:50 +01:00
Brett Foster 961abb3cf1 Avalon: Debug Clock Domain for JTAG 
This change ensures that the clock domain for the JTAG interface
uses the debug plugin's domain. Otherwise, resetting the processor
will put the jtag debugger in to reset as well.

See SpinalHDL/VexRiscv#48
 2018-12-22 07:58:59 -08:00