Dolu1990
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d73aa9ce00
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rework csr exception/interrupt handeling wip
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2018-06-24 00:14:55 +02:00 |
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Dolu1990
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8886f7e6d4
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test wip
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2018-06-19 16:15:42 +02:00 |
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Dolu1990
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1090111a6f
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TestIndividual is now fully random
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2018-06-15 13:00:59 +02:00 |
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Dolu1990
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83864710a3
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Fix IBusCached single cycle interaction with mmu bus
Add random test configs
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2018-06-09 08:40:19 +02:00 |
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Dolu1990
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08a1212fca
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Add DBus simple/cached regressions
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2018-06-07 02:31:18 +02:00 |
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Dolu1990
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6bc5431fcd
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Add iBusCached regressions
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2018-06-07 00:57:26 +02:00 |
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Dolu1990
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5e7dd02bf7
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Fix relaxedPc/DYNAMIC_TARGET interaction
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2018-06-06 18:30:30 +02:00 |
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Dolu1990
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7768f065e4
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Add many cpu configs on regressions tests (some config are broken)
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2018-06-06 02:23:07 +02:00 |
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Dolu1990
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930563291c
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Allow RVC/dynamic_target/fetch bus latency > 1 all together
Fix freeretos rvc regressions
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2018-06-05 02:21:05 +02:00 |
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Dolu1990
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9f0387350b
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Add Freertos RVC binaries regression
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2018-06-03 17:10:58 +02:00 |
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Dolu1990
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7375855e58
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DYNAMIC_PREDICTION used with RVC pass tests (1 cycle fetch)
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2018-06-03 00:50:18 +02:00 |
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Dolu1990
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5943ee727e
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Fill travis, DhrystoneBench is now a Unit test
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2018-05-28 09:02:01 +02:00 |
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Dolu1990
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9815763b7f
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Merge remote-tracking branch 'origin/master' into reworkFetcher
Conflicts:
src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
src/test/cpp/regression/main.cpp
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2018-05-24 14:04:01 +02:00 |
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Dolu1990
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2f8ccc55b6
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Fix branch plugin decode prediction exception by using the instruction decoder
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2018-05-24 12:52:00 +02:00 |
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Dolu1990
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a53f8fdc35
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Clean configs
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2018-05-23 16:57:32 +02:00 |
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Dolu1990
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acccbf40e2
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RVC debug pass tets
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2018-05-09 00:28:14 +02:00 |
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Dolu1990
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0056da1342
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DebugPlugin work
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2018-05-08 02:01:34 +02:00 |
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Dolu1990
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a50fbf0d7a
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Fix IBusCachedPlugin Pass all dhrystone tests
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2018-04-30 13:35:17 +02:00 |
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Dolu1990
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6598e82920
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wishbone => word address, not byte address
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2018-04-19 11:22:06 +02:00 |
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Dolu1990
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455607b6b4
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Fix dBus IO access
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2018-04-18 14:11:59 +02:00 |
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Dolu1990
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6e59ddcc73
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Cached wishbone demo is passing regression tests
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2018-04-18 13:51:33 +02:00 |
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Dolu1990
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76352b44fa
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wip
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2018-04-13 12:51:27 +02:00 |
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Dolu1990
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c48c7170e8
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Added many pipelining option into IBusSimplePlugin
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2018-03-23 19:07:03 +01:00 |
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Dolu1990
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351ad10925
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RVC Add dhrystone regressions (PASS)
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2018-03-21 23:36:57 +01:00 |
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Dolu1990
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0c7c2a1fba
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IBusPlugin add support of bus error when using compressed instruction
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2018-03-21 22:34:54 +01:00 |
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Dolu1990
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31a464ffdc
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VexRiscv now pass Riscv-test compressed stuff
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2018-03-21 20:50:07 +01:00 |
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Dolu1990
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af638e7bde
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RV32IC is passing some of the compressed Riscv-test tests
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2018-03-21 20:30:09 +01:00 |
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Dolu1990
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1fb138de1f
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IBusSimplePlugin fully functional Need to restore branch prediction
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2018-03-20 00:01:28 +01:00 |
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Dolu1990
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ac74fb9ce8
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iBusSimplePlugin done, DebugPlugin need minor rework
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2018-03-18 13:21:21 +01:00 |
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Dolu1990
|
5228a53293
|
MuraxSim improve simulation Speed
|
2018-03-06 12:20:39 +01:00 |
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Dolu1990
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9b2cd7b234
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MuraxSim add switch
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2018-03-06 12:17:15 +01:00 |
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Dolu1990
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5260ad5c35
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Decoding lib cleaning
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2018-02-25 08:57:31 +01:00 |
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Dolu1990
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137b1ee32c
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Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values
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2018-02-22 22:36:13 +01:00 |
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Dolu1990
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d0e963559a
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Update readme with the new ICache implementation
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2018-02-18 23:48:11 +01:00 |
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Dolu1990
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93110d3b95
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Add jump priority managment in PcPlugins
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2018-02-16 14:27:20 +01:00 |
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Dolu1990
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506e0e3f60
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New faster/smaller/multi way instruction cache design.
Single or dual stage
|
2018-02-16 02:21:08 +01:00 |
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Dolu1990
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3ee111e100
|
Update readme (gcc stuff)
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2018-02-05 16:34:10 +01:00 |
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Dolu1990
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d4b05ea365
|
Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location
Commit missing file
Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
|
2018-02-05 16:16:27 +01:00 |
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Dolu1990
|
b7d8ed8a81
|
Add onWrite/onRead/isWriting/isReading on the CsrPlugin
|
2018-02-01 21:28:28 +01:00 |
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Dolu1990
|
4ee2482cbf
|
Fix custom_csr regression against random ibus stall
|
2018-01-31 18:33:21 +01:00 |
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Dolu1990
|
30b05eaf96
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Add CsrInterface to allow custom CSR addition
Add CustomCsrDemoPlugin as a show case
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2018-01-31 18:13:42 +01:00 |
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Dolu1990
|
bdbf6ecf17
|
BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions
|
2018-01-29 14:52:31 +01:00 |
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Dolu1990
|
0d318ab6b9
|
Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz)
Add longer timeouts in the regressions tests
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2018-01-29 13:17:11 +01:00 |
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Dolu1990
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93da5d29bc
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Fix dhrystone referance log
|
2018-01-28 16:34:55 +01:00 |
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Dolu1990
|
26732942e5
|
Update DMIPS/Mhz
Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
|
2018-01-25 01:11:57 +01:00 |
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Dolu1990
|
3b3bbd48b9
|
SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
|
2018-01-20 18:29:33 +01:00 |
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Dolu1990
|
6a521a8d13
|
Better MuraxSim gui
Add MuraxSim in the readme
|
2018-01-09 08:59:17 +01:00 |
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Dolu1990
|
43d3ffd685
|
CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure
|
2018-01-04 17:37:23 +01:00 |
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Dolu1990
|
2b7465e5df
|
Add more atomic tests (PASS)
|
2018-01-04 16:16:22 +01:00 |
|
Dolu1990
|
611f2f487f
|
Fix DataCache atomic integration into DBusCachedPlugin
Atomic is passing basic tests
|
2018-01-04 15:24:00 +01:00 |